1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Roseapple Pi 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "owl-s500.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "roseapplepi,roseapplepi", "actions,s500"; 14*4882a593Smuzhiyun model = "Roseapple Pi"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun serial2 = &uart2; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun stdout-path = "serial2:115200n8"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@0 { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0x0 0x80000000>; /* 2GB */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun uart2_clk: uart2-clk { 30*4882a593Smuzhiyun compatible = "fixed-clock"; 31*4882a593Smuzhiyun clock-frequency = <921600>; 32*4882a593Smuzhiyun #clock-cells = <0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&twd_timer { 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&timer { 41*4882a593Smuzhiyun clocks = <&hosc>; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&uart2 { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun clocks = <&uart2_clk>; 47*4882a593Smuzhiyun}; 48