1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 12*4882a593Smuzhiyun#include "orion5x-mv88f5182.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Marvell Reference Design 88F5182 NAS"; 16*4882a593Smuzhiyun compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x00000000 0x4000000>; /* 64 MB */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun chosen { 24*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8 earlyprintk"; 25*4882a593Smuzhiyun stdout-path = &uart0; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun soc { 29*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, 30*4882a593Smuzhiyun <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, 31*4882a593Smuzhiyun <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>, 32*4882a593Smuzhiyun <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun gpio-leds { 36*4882a593Smuzhiyun compatible = "gpio-leds"; 37*4882a593Smuzhiyun pinctrl-0 = <&pmx_debug_led>; 38*4882a593Smuzhiyun pinctrl-names = "default"; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun led@0 { 41*4882a593Smuzhiyun label = "rd88f5182:cpu"; 42*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 43*4882a593Smuzhiyun gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&devbus_bootcs { 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Read parameters */ 52*4882a593Smuzhiyun devbus,bus-width = <8>; 53*4882a593Smuzhiyun devbus,turn-off-ps = <90000>; 54*4882a593Smuzhiyun devbus,badr-skew-ps = <0>; 55*4882a593Smuzhiyun devbus,acc-first-ps = <186000>; 56*4882a593Smuzhiyun devbus,acc-next-ps = <186000>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Write parameters */ 59*4882a593Smuzhiyun devbus,wr-high-ps = <90000>; 60*4882a593Smuzhiyun devbus,wr-low-ps = <90000>; 61*4882a593Smuzhiyun devbus,ale-wr-ps = <90000>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun flash@0 { 64*4882a593Smuzhiyun compatible = "cfi-flash"; 65*4882a593Smuzhiyun reg = <0 0x80000>; 66*4882a593Smuzhiyun bank-width = <1>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&devbus_cs1 { 71*4882a593Smuzhiyun status = "okay"; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Read parameters */ 74*4882a593Smuzhiyun devbus,bus-width = <8>; 75*4882a593Smuzhiyun devbus,turn-off-ps = <90000>; 76*4882a593Smuzhiyun devbus,badr-skew-ps = <0>; 77*4882a593Smuzhiyun devbus,acc-first-ps = <186000>; 78*4882a593Smuzhiyun devbus,acc-next-ps = <186000>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Write parameters */ 81*4882a593Smuzhiyun devbus,wr-high-ps = <90000>; 82*4882a593Smuzhiyun devbus,wr-low-ps = <90000>; 83*4882a593Smuzhiyun devbus,ale-wr-ps = <90000>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun flash@0 { 86*4882a593Smuzhiyun compatible = "cfi-flash"; 87*4882a593Smuzhiyun reg = <0 0x1000000>; 88*4882a593Smuzhiyun bank-width = <1>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&ehci0 { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&ehci1 { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyunð { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun ethernet-port@0 { 104*4882a593Smuzhiyun phy-handle = <ðphy>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&i2c { 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun clock-frequency = <100000>; 111*4882a593Smuzhiyun #address-cells = <1>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun rtc@68 { 114*4882a593Smuzhiyun pinctrl-0 = <&pmx_rtc>; 115*4882a593Smuzhiyun pinctrl-names = "default"; 116*4882a593Smuzhiyun compatible = "dallas,ds1338"; 117*4882a593Smuzhiyun reg = <0x68>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&mdio { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun ethphy: ethernet-phy { 125*4882a593Smuzhiyun reg = <8>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&pinctrl { 130*4882a593Smuzhiyun pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios 131*4882a593Smuzhiyun &pmx_pci_gpios>; 132*4882a593Smuzhiyun pinctrl-names = "default"; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* 135*4882a593Smuzhiyun * MPP[20] PCI Clock to MV88F5182 136*4882a593Smuzhiyun * MPP[21] PCI Clock to mini PCI CON11 137*4882a593Smuzhiyun * MPP[22] USB 0 over current indication 138*4882a593Smuzhiyun * MPP[23] USB 1 over current indication 139*4882a593Smuzhiyun * MPP[24] USB 1 over current enable 140*4882a593Smuzhiyun * MPP[25] USB 0 over current enable 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun pmx_debug_led: pmx-debug_led { 144*4882a593Smuzhiyun marvell,pins = "mpp0"; 145*4882a593Smuzhiyun marvell,function = "gpio"; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun pmx_reset_switch: pmx-reset-switch { 149*4882a593Smuzhiyun marvell,pins = "mpp1"; 150*4882a593Smuzhiyun marvell,function = "gpio"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun pmx_rtc: pmx-rtc { 154*4882a593Smuzhiyun marvell,pins = "mpp3"; 155*4882a593Smuzhiyun marvell,function = "gpio"; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun pmx_misc_gpios: pmx-misc-gpios { 159*4882a593Smuzhiyun marvell,pins = "mpp4", "mpp5"; 160*4882a593Smuzhiyun marvell,function = "gpio"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun pmx_pci_gpios: pmx-pci-gpios { 164*4882a593Smuzhiyun marvell,pins = "mpp6", "mpp7"; 165*4882a593Smuzhiyun marvell,function = "gpio"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun&sata { 170*4882a593Smuzhiyun pinctrl-0 = <&pmx_sata0 &pmx_sata1>; 171*4882a593Smuzhiyun pinctrl-names = "default"; 172*4882a593Smuzhiyun status = "okay"; 173*4882a593Smuzhiyun nr-ports = <2>; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&uart0 { 177*4882a593Smuzhiyun status = "okay"; 178*4882a593Smuzhiyun}; 179