1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "orion5x.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun soc { 15*4882a593Smuzhiyun compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun internal-regs { 18*4882a593Smuzhiyun pinctrl: pinctrl@10000 { 19*4882a593Smuzhiyun compatible = "marvell,88f5182-pinctrl"; 20*4882a593Smuzhiyun reg = <0x10000 0x8>, <0x10050 0x4>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun pmx_sata0: pmx-sata0 { 23*4882a593Smuzhiyun marvell,pins = "mpp12", "mpp14"; 24*4882a593Smuzhiyun marvell,function = "sata0"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun pmx_sata1: pmx-sata1 { 28*4882a593Smuzhiyun marvell,pins = "mpp13", "mpp15"; 29*4882a593Smuzhiyun marvell,function = "sata1"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun core_clk: core-clocks@10030 { 34*4882a593Smuzhiyun compatible = "marvell,mv88f5182-core-clock"; 35*4882a593Smuzhiyun reg = <0x10010 0x4>; 36*4882a593Smuzhiyun #clock-cells = <1>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun mbusc: mbus-controller@20000 { 40*4882a593Smuzhiyun compatible = "marvell,mbus-controller"; 41*4882a593Smuzhiyun reg = <0x20000 0x100>, <0x1500 0x20>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun}; 46