1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "orion5x.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun soc { 15*4882a593Smuzhiyun compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun internal-regs { 18*4882a593Smuzhiyun pinctrl: pinctrl@10000 { 19*4882a593Smuzhiyun compatible = "marvell,88f5181-pinctrl"; 20*4882a593Smuzhiyun reg = <0x10000 0x8>, <0x10050 0x4>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun core_clk: core-clocks@10030 { 24*4882a593Smuzhiyun compatible = "marvell,mv88f5181-core-clock"; 25*4882a593Smuzhiyun reg = <0x10010 0x4>; 26*4882a593Smuzhiyun #clock-cells = <1>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun mbusc: mbus-controller@20000 { 30*4882a593Smuzhiyun compatible = "marvell,mbus-controller"; 31*4882a593Smuzhiyun reg = <0x20000 0x100>, <0x1500 0x20>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&pinctrl { 38*4882a593Smuzhiyun pmx_ge: pmx-ge { 39*4882a593Smuzhiyun marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", 40*4882a593Smuzhiyun "mpp12", "mpp13", "mpp14", "mpp15", 41*4882a593Smuzhiyun "mpp16", "mpp17", "mpp18", "mpp19"; 42*4882a593Smuzhiyun marvell,function = "ge"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunð { 47*4882a593Smuzhiyun pinctrl-0 = <&pmx_ge>; 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun}; 50