1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree Source for OMAP443x SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License 7*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any 8*4882a593Smuzhiyun * kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "omap4.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun cpus { 15*4882a593Smuzhiyun cpu0: cpu@0 { 16*4882a593Smuzhiyun /* OMAP443x variants OPP50-OPPNT */ 17*4882a593Smuzhiyun operating-points = < 18*4882a593Smuzhiyun /* kHz uV */ 19*4882a593Smuzhiyun 300000 1025000 20*4882a593Smuzhiyun 600000 1200000 21*4882a593Smuzhiyun 800000 1313000 22*4882a593Smuzhiyun 1008000 1375000 23*4882a593Smuzhiyun >; 24*4882a593Smuzhiyun clock-latency = <300000>; /* From legacy driver */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* cooling options */ 27*4882a593Smuzhiyun #cooling-cells = <2>; /* min followed by max */ 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun thermal-zones { 32*4882a593Smuzhiyun #include "omap4-cpu-thermal.dtsi" 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun ocp { 36*4882a593Smuzhiyun /* 4430 has only gpio_86 tshut and no talert interrupt */ 37*4882a593Smuzhiyun bandgap: bandgap@4a002260 { 38*4882a593Smuzhiyun reg = <0x4a002260 0x4 39*4882a593Smuzhiyun 0x4a00232C 0x4>; 40*4882a593Smuzhiyun compatible = "ti,omap4430-bandgap"; 41*4882a593Smuzhiyun gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #thermal-sensor-cells = <0>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ocp { 48*4882a593Smuzhiyun abb_mpu: regulator-abb-mpu { 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>; 52*4882a593Smuzhiyun reg-names = "base-address", "int-address"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ti,abb_info = < 55*4882a593Smuzhiyun /*uV ABB efuse rbb_m fbb_m vset_m*/ 56*4882a593Smuzhiyun 1025000 0 0 0 0 0 57*4882a593Smuzhiyun 1200000 0 0 0 0 0 58*4882a593Smuzhiyun 1313000 0 0 0 0 0 59*4882a593Smuzhiyun 1375000 1 0 0 0 0 60*4882a593Smuzhiyun 1389000 1 0 0 0 0 61*4882a593Smuzhiyun >; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Default unused, just provide register info for record */ 65*4882a593Smuzhiyun abb_iva: regulator-abb-iva { 66*4882a593Smuzhiyun reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>; 67*4882a593Smuzhiyun reg-names = "base-address", "int-address"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&cpu_thermal { 75*4882a593Smuzhiyun coefficients = <0 20000>; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun/include/ "omap443x-clocks.dtsi" 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun/* 81*4882a593Smuzhiyun * Use dpll_per for sgx at 153.6MHz like droid4 stock v3.0.8 Android kernel 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun&sgx_module { 84*4882a593Smuzhiyun assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>, 85*4882a593Smuzhiyun <&dpll_per_m7x2_ck>; 86*4882a593Smuzhiyun assigned-clock-rates = <0>, <153600000>; 87*4882a593Smuzhiyun assigned-clock-parents = <&dpll_per_m7x2_ck>; 88*4882a593Smuzhiyun}; 89