1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun /* regulator for wl12xx on sdio4 */ 8*4882a593Smuzhiyun wl12xx_vmmc: wl12xx_vmmc { 9*4882a593Smuzhiyun pinctrl-names = "default"; 10*4882a593Smuzhiyun pinctrl-0 = <&wl12xx_ctrl_pins>; 11*4882a593Smuzhiyun compatible = "regulator-fixed"; 12*4882a593Smuzhiyun regulator-name = "vwl1271"; 13*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 14*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 15*4882a593Smuzhiyun gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* gpio 43 */ 16*4882a593Smuzhiyun startup-delay-us = <70000>; 17*4882a593Smuzhiyun enable-active-high; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&omap4_pmx_core { 22*4882a593Smuzhiyun uart2_pins: pinmux_uart2_pins { 23*4882a593Smuzhiyun pinctrl-single,pins = < 24*4882a593Smuzhiyun OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 25*4882a593Smuzhiyun OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 26*4882a593Smuzhiyun OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ 27*4882a593Smuzhiyun OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 28*4882a593Smuzhiyun >; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { 32*4882a593Smuzhiyun pinctrl-single,pins = < 33*4882a593Smuzhiyun OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ 34*4882a593Smuzhiyun OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ 35*4882a593Smuzhiyun OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ 36*4882a593Smuzhiyun >; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun mmc4_pins: pinmux_mmc4_pins { 40*4882a593Smuzhiyun pinctrl-single,pins = < 41*4882a593Smuzhiyun OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ 42*4882a593Smuzhiyun OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ 43*4882a593Smuzhiyun OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ 44*4882a593Smuzhiyun OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ 45*4882a593Smuzhiyun OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ 46*4882a593Smuzhiyun OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ 47*4882a593Smuzhiyun >; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&uart2 { 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&mmc4 { 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&mmc4_pins>; 60*4882a593Smuzhiyun vmmc-supply = <&wl12xx_vmmc>; 61*4882a593Smuzhiyun non-removable; 62*4882a593Smuzhiyun bus-width = <4>; 63*4882a593Smuzhiyun cap-power-off-card; 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun wlcore: wlcore@2 { 69*4882a593Smuzhiyun compatible = "ti,wl1271"; 70*4882a593Smuzhiyun reg = <2>; 71*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 72*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ 73*4882a593Smuzhiyun ref-clock-frequency = <38400000>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76