1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Common omap4 mcpdm configuration 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Only include this file if your board has pdmclk wired from the 6*4882a593Smuzhiyun * pmic to ABE as mcpdm uses an external clock for the module. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun&omap4_pmx_core { 10*4882a593Smuzhiyun mcpdm_pins: pinmux_mcpdm_pins { 11*4882a593Smuzhiyun pinctrl-single,pins = < 12*4882a593Smuzhiyun /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ 13*4882a593Smuzhiyun OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */ 16*4882a593Smuzhiyun OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */ 19*4882a593Smuzhiyun OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */ 22*4882a593Smuzhiyun OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 0x4a10010e abe_clks.abe_clks ah26 */ 25*4882a593Smuzhiyun OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) 26*4882a593Smuzhiyun >; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&mcpdm_module { 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * McPDM pads must be muxed at the interconnect target module 33*4882a593Smuzhiyun * level as the module on the SoC needs external clock from 34*4882a593Smuzhiyun * the PMIC 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun pinctrl-names = "default"; 37*4882a593Smuzhiyun pinctrl-0 = <&mcpdm_pins>; 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&mcpdm { 42*4882a593Smuzhiyun clocks = <&twl6040>; 43*4882a593Smuzhiyun clock-names = "pdmclk"; 44*4882a593Smuzhiyun}; 45