1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "omap36xx.dtsi" 8*4882a593Smuzhiyun#include "omap-zoom-common.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "TI Zoom3"; 12*4882a593Smuzhiyun compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun cpus { 15*4882a593Smuzhiyun cpu@0 { 16*4882a593Smuzhiyun cpu0-supply = <&vcc>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory@80000000 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; /* 512 MB */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun vddvario: regulator-vddvario { 26*4882a593Smuzhiyun compatible = "regulator-fixed"; 27*4882a593Smuzhiyun regulator-name = "vddvario"; 28*4882a593Smuzhiyun regulator-always-on; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun vdd33a: regulator-vdd33a { 32*4882a593Smuzhiyun compatible = "regulator-fixed"; 33*4882a593Smuzhiyun regulator-name = "vdd33a"; 34*4882a593Smuzhiyun regulator-always-on; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun wl12xx_vmmc: wl12xx_vmmc { 38*4882a593Smuzhiyun pinctrl-names = "default"; 39*4882a593Smuzhiyun pinctrl-0 = <&wl12xx_gpio>; 40*4882a593Smuzhiyun compatible = "regulator-fixed"; 41*4882a593Smuzhiyun regulator-name = "vwl1271"; 42*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 43*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 44*4882a593Smuzhiyun gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ 45*4882a593Smuzhiyun startup-delay-us = <70000>; 46*4882a593Smuzhiyun enable-active-high; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&omap3_pmx_core { 51*4882a593Smuzhiyun /* REVISIT: twl gpio0 is mmc0_cd */ 52*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 53*4882a593Smuzhiyun pinctrl-single,pins = < 54*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 55*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 56*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 57*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 58*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 59*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 60*4882a593Smuzhiyun >; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun mmc2_pins: pinmux_mmc2_pins { 64*4882a593Smuzhiyun pinctrl-single,pins = < 65*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 66*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 67*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 68*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 69*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 70*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 71*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ 72*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ 73*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ 74*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun mmc3_pins: pinmux_mmc3_pins { 79*4882a593Smuzhiyun pinctrl-single,pins = < 80*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ 81*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ 82*4882a593Smuzhiyun >; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun uart1_pins: pinmux_uart1_pins { 86*4882a593Smuzhiyun pinctrl-single,pins = < 87*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ 88*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ 89*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 90*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ 91*4882a593Smuzhiyun >; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun uart2_pins: pinmux_uart2_pins { 95*4882a593Smuzhiyun pinctrl-single,pins = < 96*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ 97*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ 98*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 99*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 100*4882a593Smuzhiyun >; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun uart3_pins: pinmux_uart3_pins { 104*4882a593Smuzhiyun pinctrl-single,pins = < 105*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ 106*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ 107*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 108*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 109*4882a593Smuzhiyun >; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* wl12xx GPIO output for WLAN_EN */ 113*4882a593Smuzhiyun wl12xx_gpio: pinmux_wl12xx_gpio { 114*4882a593Smuzhiyun pinctrl-single,pins = < 115*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ 116*4882a593Smuzhiyun >; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&omap3_pmx_core2 { 121*4882a593Smuzhiyun mmc3_2_pins: pinmux_mmc3_2_pins { 122*4882a593Smuzhiyun pinctrl-single,pins = < 123*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ 124*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ 125*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ 126*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ 127*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ 128*4882a593Smuzhiyun >; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&omap3_pmx_wkup { 133*4882a593Smuzhiyun wlan_host_wkup: pinmux_wlan_host_wkup_pins { 134*4882a593Smuzhiyun pinctrl-single,pins = < 135*4882a593Smuzhiyun OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ 136*4882a593Smuzhiyun >; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&i2c1 { 141*4882a593Smuzhiyun clock-frequency = <2600000>; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun twl: twl@48 { 144*4882a593Smuzhiyun reg = <0x48>; 145*4882a593Smuzhiyun interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 146*4882a593Smuzhiyun interrupt-parent = <&intc>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun#include "twl4030.dtsi" 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&i2c2 { 153*4882a593Smuzhiyun clock-frequency = <400000>; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&i2c3 { 157*4882a593Smuzhiyun clock-frequency = <400000>; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* 160*4882a593Smuzhiyun * TVP5146 Video decoder-in for analog input support. 161*4882a593Smuzhiyun */ 162*4882a593Smuzhiyun tvp5146@5c { 163*4882a593Smuzhiyun compatible = "ti,tvp5146m2"; 164*4882a593Smuzhiyun reg = <0x5c>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun}; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun&twl_gpio { 169*4882a593Smuzhiyun ti,use-leds; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&mmc1 { 173*4882a593Smuzhiyun vmmc-supply = <&vmmc1>; 174*4882a593Smuzhiyun vqmmc-supply = <&vsim>; 175*4882a593Smuzhiyun bus-width = <4>; 176*4882a593Smuzhiyun pinctrl-names = "default"; 177*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun/* 180*4882a593Smuzhiyun&mmc2 { 181*4882a593Smuzhiyun vmmc-supply = <&vmmc2>; 182*4882a593Smuzhiyun ti,non-removable; 183*4882a593Smuzhiyun bus-width = <8>; 184*4882a593Smuzhiyun pinctrl-names = "default"; 185*4882a593Smuzhiyun pinctrl-0 = <&mmc2_pins>; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun*/ 188*4882a593Smuzhiyun&mmc3 { 189*4882a593Smuzhiyun vmmc-supply = <&wl12xx_vmmc>; 190*4882a593Smuzhiyun non-removable; 191*4882a593Smuzhiyun bus-width = <4>; 192*4882a593Smuzhiyun cap-power-off-card; 193*4882a593Smuzhiyun pinctrl-names = "default"; 194*4882a593Smuzhiyun pinctrl-0 = <&mmc3_pins &mmc3_2_pins>; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #address-cells = <1>; 197*4882a593Smuzhiyun #size-cells = <0>; 198*4882a593Smuzhiyun wlcore: wlcore@2 { 199*4882a593Smuzhiyun compatible = "ti,wl1271"; 200*4882a593Smuzhiyun reg = <2>; 201*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 202*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ 203*4882a593Smuzhiyun ref-clock-frequency = <26000000>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun}; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun&uart1 { 208*4882a593Smuzhiyun pinctrl-names = "default"; 209*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&uart2 { 213*4882a593Smuzhiyun pinctrl-names = "default"; 214*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 215*4882a593Smuzhiyun}; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun&uart3 { 218*4882a593Smuzhiyun pinctrl-names = "default"; 219*4882a593Smuzhiyun pinctrl-0 = <&uart3_pins>; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&uart4 { 223*4882a593Smuzhiyun status = "disabled"; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&usb_otg_hs { 227*4882a593Smuzhiyun interface-type = <0>; 228*4882a593Smuzhiyun usb-phy = <&usb2_phy>; 229*4882a593Smuzhiyun mode = <3>; 230*4882a593Smuzhiyun power = <50>; 231*4882a593Smuzhiyun}; 232