1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun lis33_3v3: lis33-3v3-reg { 12*4882a593Smuzhiyun compatible = "regulator-fixed"; 13*4882a593Smuzhiyun regulator-name = "lis33-3v3-reg"; 14*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 15*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun lis33_1v8: lis33-1v8-reg { 19*4882a593Smuzhiyun compatible = "regulator-fixed"; 20*4882a593Smuzhiyun regulator-name = "lis33-1v8-reg"; 21*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 22*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun}; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun&omap3_pmx_core { 27*4882a593Smuzhiyun i2c3_pins: pinmux_i2c3_pins { 28*4882a593Smuzhiyun pinctrl-single,pins = < 29*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ 30*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ 31*4882a593Smuzhiyun >; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun uart3_pins: pinmux_uart3_pins { 35*4882a593Smuzhiyun pinctrl-single,pins = < 36*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 37*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 38*4882a593Smuzhiyun >; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&i2c3 { 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&i2c3_pins>; 45*4882a593Smuzhiyun clock-frequency = <100000>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* optional 1K EEPROM with revision information */ 48*4882a593Smuzhiyun eeprom@51 { 49*4882a593Smuzhiyun compatible = "atmel,24c01"; 50*4882a593Smuzhiyun reg = <0x51>; 51*4882a593Smuzhiyun pagesize = <8>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun lis33de: lis33de@1d { 55*4882a593Smuzhiyun compatible = "st,lis33de", "st,lis3lv02d"; 56*4882a593Smuzhiyun reg = <0x1d>; 57*4882a593Smuzhiyun Vdd-supply = <&lis33_1v8>; 58*4882a593Smuzhiyun Vdd_IO-supply = <&lis33_3v3>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun st,click-single-x; 61*4882a593Smuzhiyun st,click-single-y; 62*4882a593Smuzhiyun st,click-single-z; 63*4882a593Smuzhiyun st,click-thresh-x = <10>; 64*4882a593Smuzhiyun st,click-thresh-y = <10>; 65*4882a593Smuzhiyun st,click-thresh-z = <10>; 66*4882a593Smuzhiyun st,irq1-click; 67*4882a593Smuzhiyun st,irq2-click; 68*4882a593Smuzhiyun st,wakeup-x-lo; 69*4882a593Smuzhiyun st,wakeup-x-hi; 70*4882a593Smuzhiyun st,wakeup-y-lo; 71*4882a593Smuzhiyun st,wakeup-y-hi; 72*4882a593Smuzhiyun st,wakeup-z-lo; 73*4882a593Smuzhiyun st,wakeup-z-hi; 74*4882a593Smuzhiyun st,min-limit-x = <120>; 75*4882a593Smuzhiyun st,min-limit-y = <120>; 76*4882a593Smuzhiyun st,min-limit-z = <140>; 77*4882a593Smuzhiyun st,max-limit-x = <550>; 78*4882a593Smuzhiyun st,max-limit-y = <550>; 79*4882a593Smuzhiyun st,max-limit-z = <750>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&mmc3 { 84*4882a593Smuzhiyun status = "disabled"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&uart3 { 88*4882a593Smuzhiyun interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 89*4882a593Smuzhiyun pinctrl-names = "default"; 90*4882a593Smuzhiyun pinctrl-0 = <&uart3_pins>; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93