xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/omap3-overo-base.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/*
7*4882a593Smuzhiyun * The Gumstix Overo must be combined with an expansion board.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun	memory@0 {
13*4882a593Smuzhiyun		device_type = "memory";
14*4882a593Smuzhiyun		reg = <0 0>;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	pwmleds {
18*4882a593Smuzhiyun		compatible = "pwm-leds";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun		overo {
21*4882a593Smuzhiyun			label = "overo:blue:COM";
22*4882a593Smuzhiyun			pwms = <&twl_pwmled 1 7812500>;
23*4882a593Smuzhiyun			max-brightness = <127>;
24*4882a593Smuzhiyun			linux,default-trigger = "mmc0";
25*4882a593Smuzhiyun		};
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	sound {
29*4882a593Smuzhiyun		compatible = "ti,omap-twl4030";
30*4882a593Smuzhiyun		ti,model = "overo";
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		ti,mcbsp = <&mcbsp2>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	/* HS USB Port 2 Power */
36*4882a593Smuzhiyun	hsusb2_power: hsusb2_power_reg {
37*4882a593Smuzhiyun		compatible = "regulator-fixed";
38*4882a593Smuzhiyun		regulator-name = "hsusb2_vbus";
39*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
40*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
41*4882a593Smuzhiyun		gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>;		/* gpio_168: vbus enable */
42*4882a593Smuzhiyun		startup-delay-us = <70000>;
43*4882a593Smuzhiyun		enable-active-high;
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	/* HS USB Host PHY on PORT 2 */
47*4882a593Smuzhiyun	hsusb2_phy: hsusb2_phy {
48*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
49*4882a593Smuzhiyun		reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;	/* gpio_183 */
50*4882a593Smuzhiyun		vcc-supply = <&hsusb2_power>;
51*4882a593Smuzhiyun		#phy-cells = <0>;
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	/* Regulator to trigger the nPoweron signal of the Wifi module */
55*4882a593Smuzhiyun	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "regulator-w3cbw003c-npoweron";
58*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
60*4882a593Smuzhiyun		gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;		/* gpio_54: nPoweron */
61*4882a593Smuzhiyun		enable-active-high;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	/* Regulator to trigger the nReset signal of the Wifi module */
65*4882a593Smuzhiyun	w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
66*4882a593Smuzhiyun		pinctrl-names = "default";
67*4882a593Smuzhiyun		pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
68*4882a593Smuzhiyun		compatible = "regulator-fixed";
69*4882a593Smuzhiyun		regulator-name = "regulator-w3cbw003c-wifi-nreset";
70*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
71*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
72*4882a593Smuzhiyun		gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;		/* gpio_16: WiFi nReset */
73*4882a593Smuzhiyun		startup-delay-us = <10000>;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun&omap3_pmx_core {
78*4882a593Smuzhiyun	pinctrl-names = "default";
79*4882a593Smuzhiyun	pinctrl-0 = <
80*4882a593Smuzhiyun			&hsusb2_pins
81*4882a593Smuzhiyun	>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	uart2_pins: pinmux_uart2_pins {
84*4882a593Smuzhiyun		pinctrl-single,pins = <
85*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */
86*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_dr.uart2_rts */
87*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_clk.uart2_tx */
88*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)	/* mcbsp3_fsx.uart2_rx */
89*4882a593Smuzhiyun		>;
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	i2c1_pins: pinmux_i2c1_pins {
93*4882a593Smuzhiyun		pinctrl-single,pins = <
94*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)		/* i2c1_scl.i2c1_scl */
95*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)		/* i2c1_sda.i2c1_sda */
96*4882a593Smuzhiyun		>;
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	mmc1_pins: pinmux_mmc1_pins {
100*4882a593Smuzhiyun		pinctrl-single,pins = <
101*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_clk.sdmmc1_clk */
102*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_cmd.sdmmc1_cmd */
103*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat0.sdmmc1_dat0 */
104*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat1.sdmmc1_dat1 */
105*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat2.sdmmc1_dat2 */
106*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat3.sdmmc1_dat3 */
107*4882a593Smuzhiyun		>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	mmc2_pins: pinmux_mmc2_pins {
111*4882a593Smuzhiyun		pinctrl-single,pins = <
112*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_clk.sdmmc2_clk */
113*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_cmd.sdmmc2_cmd */
114*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat0.sdmmc2_dat0 */
115*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat1.sdmmc2_dat1 */
116*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat2.sdmmc2_dat2 */
117*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat3.sdmmc2_dat3 */
118*4882a593Smuzhiyun		>;
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	/* WiFi/BT combo */
122*4882a593Smuzhiyun	w3cbw003c_pins: pinmux_w3cbw003c_pins {
123*4882a593Smuzhiyun		pinctrl-single,pins = <
124*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4)		/* gpmc_ncs3.gpio_54 */
125*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
126*4882a593Smuzhiyun		>;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	hsusb2_pins: pinmux_hsusb2_pins {
130*4882a593Smuzhiyun		pinctrl-single,pins = <
131*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
132*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
133*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
134*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
135*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
136*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
137*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)		/* i2c2_scl.gpio_168 */
138*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)		/* i2c2_sda.gpio_183 */
139*4882a593Smuzhiyun		>;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&i2c1 {
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
146*4882a593Smuzhiyun	clock-frequency = <2600000>;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	twl: twl@48 {
149*4882a593Smuzhiyun		reg = <0x48>;
150*4882a593Smuzhiyun		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
151*4882a593Smuzhiyun		interrupt-parent = <&intc>;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		twl_audio: audio {
154*4882a593Smuzhiyun			compatible = "ti,twl4030-audio";
155*4882a593Smuzhiyun			codec {
156*4882a593Smuzhiyun			};
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun#include "twl4030.dtsi"
162*4882a593Smuzhiyun#include "twl4030_omap3.dtsi"
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun/* i2c2 pins are used for gpio */
165*4882a593Smuzhiyun&i2c2 {
166*4882a593Smuzhiyun	status = "disabled";
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun/* on board microSD slot */
170*4882a593Smuzhiyun&mmc1 {
171*4882a593Smuzhiyun	pinctrl-names = "default";
172*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins>;
173*4882a593Smuzhiyun	vmmc-supply = <&vmmc1>;
174*4882a593Smuzhiyun	bus-width = <4>;
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun/* optional on board WiFi */
178*4882a593Smuzhiyun&mmc2 {
179*4882a593Smuzhiyun	pinctrl-names = "default";
180*4882a593Smuzhiyun	pinctrl-0 = <&mmc2_pins>;
181*4882a593Smuzhiyun	vmmc-supply = <&w3cbw003c_npoweron>;
182*4882a593Smuzhiyun	vqmmc-supply = <&w3cbw003c_wifi_nreset>;
183*4882a593Smuzhiyun	bus-width = <4>;
184*4882a593Smuzhiyun	cap-sdio-irq;
185*4882a593Smuzhiyun	non-removable;
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&twl_gpio {
189*4882a593Smuzhiyun	ti,use-leds;
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&usb_otg_hs {
193*4882a593Smuzhiyun	interface-type = <0>;
194*4882a593Smuzhiyun	usb-phy = <&usb2_phy>;
195*4882a593Smuzhiyun	phys = <&usb2_phy>;
196*4882a593Smuzhiyun	phy-names = "usb2-phy";
197*4882a593Smuzhiyun	mode = <3>;
198*4882a593Smuzhiyun	power = <50>;
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&usbhshost {
202*4882a593Smuzhiyun	port2-mode = "ehci-phy";
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&usbhsehci {
206*4882a593Smuzhiyun	phys = <0 &hsusb2_phy>;
207*4882a593Smuzhiyun};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun&uart2 {
210*4882a593Smuzhiyun	pinctrl-names = "default";
211*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&mcbsp2 {
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&gpmc {
219*4882a593Smuzhiyun	ranges = <0 0 0x30000000 0x1000000>,	/* CS0 */
220*4882a593Smuzhiyun		 <4 0 0x2b000000 0x1000000>,	/* CS4 */
221*4882a593Smuzhiyun		 <5 0 0x2c000000 0x1000000>;	/* CS5 */
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	nand@0,0 {
224*4882a593Smuzhiyun		compatible = "ti,omap2-nand";
225*4882a593Smuzhiyun		linux,mtd-name= "micron,mt29c4g96maz";
226*4882a593Smuzhiyun		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
227*4882a593Smuzhiyun		interrupt-parent = <&gpmc>;
228*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
229*4882a593Smuzhiyun			     <1 IRQ_TYPE_NONE>;	/* termcount */
230*4882a593Smuzhiyun		nand-bus-width = <16>;
231*4882a593Smuzhiyun		gpmc,device-width = <2>;
232*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
235*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
236*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
237*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
238*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
239*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
240*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
241*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
242*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
243*4882a593Smuzhiyun		gpmc,access-ns = <64>;
244*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
245*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
246*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
247*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun		#address-cells = <1>;
250*4882a593Smuzhiyun		#size-cells = <1>;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun		partition@0 {
253*4882a593Smuzhiyun			label = "SPL";
254*4882a593Smuzhiyun			reg = <0 0x80000>; /* 512KiB */
255*4882a593Smuzhiyun		};
256*4882a593Smuzhiyun		partition@80000 {
257*4882a593Smuzhiyun			label = "U-Boot";
258*4882a593Smuzhiyun			reg = <0x80000 0x1C0000>; /* 1792KiB */
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun		partition@1c0000 {
261*4882a593Smuzhiyun			label = "Environment";
262*4882a593Smuzhiyun			reg = <0x240000 0x40000>; /* 256KiB */
263*4882a593Smuzhiyun		};
264*4882a593Smuzhiyun		partition@280000 {
265*4882a593Smuzhiyun			label = "Kernel";
266*4882a593Smuzhiyun			reg = <0x280000 0x800000>; /* 8192KiB */
267*4882a593Smuzhiyun		};
268*4882a593Smuzhiyun		partition@780000 {
269*4882a593Smuzhiyun			label = "Filesystem";
270*4882a593Smuzhiyun			reg = <0xA80000 0>;
271*4882a593Smuzhiyun			/* HACK: MTDPART_SIZ_FULL=0 so fill to end */
272*4882a593Smuzhiyun		};
273*4882a593Smuzhiyun	};
274*4882a593Smuzhiyun};
275