xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/omap3-igep0030-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Common Device Tree Source for IGEP COM MODULE
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Javier Martinez Canillas <javier@osg.samsung.com>
6*4882a593Smuzhiyun * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "omap3-igep.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	leds: gpio_leds {
13*4882a593Smuzhiyun		compatible = "gpio-leds";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun		user0 {
16*4882a593Smuzhiyun			 label = "omap3:red:user0";
17*4882a593Smuzhiyun			 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;	/* LEDA */
18*4882a593Smuzhiyun			 default-state = "off";
19*4882a593Smuzhiyun		};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		user1 {
22*4882a593Smuzhiyun			 label = "omap3:green:user1";
23*4882a593Smuzhiyun			 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;	/* LEDB */
24*4882a593Smuzhiyun			 default-state = "off";
25*4882a593Smuzhiyun		};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		user2 {
28*4882a593Smuzhiyun			 label = "omap3:red:user1";
29*4882a593Smuzhiyun			 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;		/* gpio_16 */
30*4882a593Smuzhiyun			 default-state = "off";
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	hsusb2_phy: hsusb2_phy {
35*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
36*4882a593Smuzhiyun		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;		/* gpio_54 */
37*4882a593Smuzhiyun		#phy-cells = <0>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun&omap3_pmx_core {
42*4882a593Smuzhiyun	pinctrl-names = "default";
43*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_pins>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	hsusb2_pins: pinmux_hsusb2_pins {
46*4882a593Smuzhiyun		pinctrl-single,pins = <
47*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
48*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
49*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
50*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
51*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
52*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
53*4882a593Smuzhiyun		>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	uart2_pins: pinmux_uart2_pins {
57*4882a593Smuzhiyun		pinctrl-single,pins = <
58*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */
59*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_dr.uart2_rts */
60*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_clk.uart2_tx */
61*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)	/* mcbsp3_fsx.uart2_rx */
62*4882a593Smuzhiyun		>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&omap3_pmx_core2 {
67*4882a593Smuzhiyun	pinctrl-names = "default";
68*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_core2_pins>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
71*4882a593Smuzhiyun		pinctrl-single,pins = <
72*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		      /* etk_d10.hsusb2_clk */
73*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		      /* etk_d11.hsusb2_stp */
74*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
75*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
76*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
77*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
78*4882a593Smuzhiyun		>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	leds_core2_pins: pinmux_leds_core2_pins {
82*4882a593Smuzhiyun		pinctrl-single,pins = <
83*4882a593Smuzhiyun			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)	/* etk_d2.gpio_16 */
84*4882a593Smuzhiyun		>;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&usbhshost {
89*4882a593Smuzhiyun	port2-mode = "ehci-phy";
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&usbhsehci {
93*4882a593Smuzhiyun	phys = <0 &hsusb2_phy>;
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun&uart2 {
97*4882a593Smuzhiyun	pinctrl-names = "default";
98*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
99*4882a593Smuzhiyun};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun&gpmc {
102*4882a593Smuzhiyun	ranges = <0 0 0x30000000 0x01000000>;   /* CS0: 16MB for NAND */
103*4882a593Smuzhiyun};
104