1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Common device tree for IGEP boards based on AM/DM37x 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com> 6*4882a593Smuzhiyun * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "omap36xx.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun memory@80000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; /* 512 MB */ 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun stdout-path = &uart3; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun sound { 23*4882a593Smuzhiyun compatible = "ti,omap-twl4030"; 24*4882a593Smuzhiyun ti,model = "igep2"; 25*4882a593Smuzhiyun ti,mcbsp = <&mcbsp2>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun vdd33: regulator-vdd33 { 29*4882a593Smuzhiyun compatible = "regulator-fixed"; 30*4882a593Smuzhiyun regulator-name = "vdd33"; 31*4882a593Smuzhiyun regulator-always-on; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&omap3_pmx_core { 37*4882a593Smuzhiyun gpmc_pins: pinmux_gpmc_pins { 38*4882a593Smuzhiyun pinctrl-single,pins = < 39*4882a593Smuzhiyun /* OneNAND seems to require PIN_INPUT on clock. */ 40*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ 41*4882a593Smuzhiyun >; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun uart1_pins: pinmux_uart1_pins { 45*4882a593Smuzhiyun pinctrl-single,pins = < 46*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 47*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ 48*4882a593Smuzhiyun >; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun uart3_pins: pinmux_uart3_pins { 52*4882a593Smuzhiyun pinctrl-single,pins = < 53*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 54*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ 55*4882a593Smuzhiyun >; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun mcbsp2_pins: pinmux_mcbsp2_pins { 59*4882a593Smuzhiyun pinctrl-single,pins = < 60*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ 61*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ 62*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ 63*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ 64*4882a593Smuzhiyun >; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 68*4882a593Smuzhiyun pinctrl-single,pins = < 69*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 70*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 71*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 72*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 73*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 74*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun mmc2_pins: pinmux_mmc2_pins { 79*4882a593Smuzhiyun pinctrl-single,pins = < 80*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 81*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 82*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 83*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 84*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 85*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 86*4882a593Smuzhiyun >; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun i2c1_pins: pinmux_i2c1_pins { 90*4882a593Smuzhiyun pinctrl-single,pins = < 91*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 92*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ 93*4882a593Smuzhiyun >; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun i2c3_pins: pinmux_i2c3_pins { 97*4882a593Smuzhiyun pinctrl-single,pins = < 98*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ 99*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ 100*4882a593Smuzhiyun >; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&gpmc { 105*4882a593Smuzhiyun pinctrl-names = "default"; 106*4882a593Smuzhiyun pinctrl-0 = <&gpmc_pins>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun nand@0,0 { 109*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 110*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 111*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 112*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 113*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 114*4882a593Smuzhiyun linux,mtd-name= "micron,mt29c4g96maz"; 115*4882a593Smuzhiyun nand-bus-width = <16>; 116*4882a593Smuzhiyun gpmc,device-width = <2>; 117*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 120*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 121*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 122*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 123*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 124*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 125*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 126*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 127*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 128*4882a593Smuzhiyun gpmc,access-ns = <64>; 129*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 130*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 131*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 132*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #address-cells = <1>; 135*4882a593Smuzhiyun #size-cells = <1>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun onenand@0,0 { 141*4882a593Smuzhiyun compatible = "ti,omap2-onenand"; 142*4882a593Smuzhiyun reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun gpmc,sync-read; 145*4882a593Smuzhiyun gpmc,sync-write; 146*4882a593Smuzhiyun gpmc,burst-length = <16>; 147*4882a593Smuzhiyun gpmc,burst-wrap; 148*4882a593Smuzhiyun gpmc,burst-read; 149*4882a593Smuzhiyun gpmc,burst-write; 150*4882a593Smuzhiyun gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ 151*4882a593Smuzhiyun gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ 152*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 153*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <96>; 154*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <96>; 155*4882a593Smuzhiyun gpmc,adv-on-ns = <0>; 156*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <12>; 157*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <12>; 158*4882a593Smuzhiyun gpmc,oe-on-ns = <18>; 159*4882a593Smuzhiyun gpmc,oe-off-ns = <96>; 160*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 161*4882a593Smuzhiyun gpmc,we-off-ns = <96>; 162*4882a593Smuzhiyun gpmc,rd-cycle-ns = <114>; 163*4882a593Smuzhiyun gpmc,wr-cycle-ns = <114>; 164*4882a593Smuzhiyun gpmc,access-ns = <90>; 165*4882a593Smuzhiyun gpmc,page-burst-access-ns = <12>; 166*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 167*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 168*4882a593Smuzhiyun gpmc,wait-monitoring-ns = <0>; 169*4882a593Smuzhiyun gpmc,clk-activation-ns = <6>; 170*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <30>; 171*4882a593Smuzhiyun gpmc,wr-access-ns = <90>; 172*4882a593Smuzhiyun gpmc,sync-clk-ps = <12000>; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #address-cells = <1>; 175*4882a593Smuzhiyun #size-cells = <1>; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun status = "disabled"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun}; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun&i2c1 { 182*4882a593Smuzhiyun pinctrl-names = "default"; 183*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 184*4882a593Smuzhiyun clock-frequency = <2600000>; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun twl: twl@48 { 187*4882a593Smuzhiyun reg = <0x48>; 188*4882a593Smuzhiyun interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 189*4882a593Smuzhiyun interrupt-parent = <&intc>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun twl_audio: audio { 192*4882a593Smuzhiyun compatible = "ti,twl4030-audio"; 193*4882a593Smuzhiyun codec { 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun#include "twl4030.dtsi" 200*4882a593Smuzhiyun#include "twl4030_omap3.dtsi" 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun&i2c3 { 203*4882a593Smuzhiyun pinctrl-names = "default"; 204*4882a593Smuzhiyun pinctrl-0 = <&i2c3_pins>; 205*4882a593Smuzhiyun}; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun&mcbsp2 { 208*4882a593Smuzhiyun pinctrl-names = "default"; 209*4882a593Smuzhiyun pinctrl-0 = <&mcbsp2_pins>; 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&mmc1 { 214*4882a593Smuzhiyun pinctrl-names = "default"; 215*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 216*4882a593Smuzhiyun vmmc-supply = <&vmmc1>; 217*4882a593Smuzhiyun vmmc_aux-supply = <&vsim>; 218*4882a593Smuzhiyun bus-width = <4>; 219*4882a593Smuzhiyun cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&mmc3 { 223*4882a593Smuzhiyun status = "disabled"; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&uart1 { 227*4882a593Smuzhiyun pinctrl-names = "default"; 228*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 229*4882a593Smuzhiyun}; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun&uart3 { 232*4882a593Smuzhiyun pinctrl-names = "default"; 233*4882a593Smuzhiyun pinctrl-0 = <&uart3_pins>; 234*4882a593Smuzhiyun}; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun&twl_gpio { 237*4882a593Smuzhiyun ti,use-leds; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun&usb_otg_hs { 241*4882a593Smuzhiyun interface-type = <0>; 242*4882a593Smuzhiyun usb-phy = <&usb2_phy>; 243*4882a593Smuzhiyun phys = <&usb2_phy>; 244*4882a593Smuzhiyun phy-names = "usb2-phy"; 245*4882a593Smuzhiyun mode = <3>; 246*4882a593Smuzhiyun power = <50>; 247*4882a593Smuzhiyun}; 248