1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun * Copyright (C) 2014 Stefan Roese <sr@denx.de> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "omap3-ha-common.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; 11*4882a593Smuzhiyun compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3"; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&omap3_pmx_core { 15*4882a593Smuzhiyun pinctrl-names = "default"; 16*4882a593Smuzhiyun pinctrl-0 = < 17*4882a593Smuzhiyun &hsusbb2_pins 18*4882a593Smuzhiyun &powerdown_input_pins 19*4882a593Smuzhiyun &fpga_boot0_pins 20*4882a593Smuzhiyun &fpga_boot1_pins 21*4882a593Smuzhiyun &led_blue_pins 22*4882a593Smuzhiyun &led_green_pins 23*4882a593Smuzhiyun &led_red_pins 24*4882a593Smuzhiyun &touchscreen_wake_pins 25*4882a593Smuzhiyun >; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun touchscreen_irq_pins: pinmux_touchscreen_irq_pins { 28*4882a593Smuzhiyun pinctrl-single,pins = < 29*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ 30*4882a593Smuzhiyun >; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun touchscreen_wake_pins: pinmux_touchscreen_wake_pins { 34*4882a593Smuzhiyun pinctrl-single,pins = < 35*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ 36*4882a593Smuzhiyun >; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun dss_dpi_pins: pinmux_dss_dpi_pins { 40*4882a593Smuzhiyun pinctrl-single,pins = < 41*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 42*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 43*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 44*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 45*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 46*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 47*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 48*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 49*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 50*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 51*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 52*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 53*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 54*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 55*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 56*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 57*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 58*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 59*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 60*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 61*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 62*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 63*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 64*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 65*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 66*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 67*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 68*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 69*4882a593Smuzhiyun >; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun lte430_pins: pinmux_lte430_pins { 73*4882a593Smuzhiyun pinctrl-single,pins = < 74*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun backlight_pins: pinmux_backlight_pins { 79*4882a593Smuzhiyun pinctrl-single,pins = < 80*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ 81*4882a593Smuzhiyun >; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ 86*4882a593Smuzhiyun&i2c2 { 87*4882a593Smuzhiyun status = "disabled"; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&i2c3 { 91*4882a593Smuzhiyun clock-frequency = <100000>; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun pinctrl-names = "default"; 94*4882a593Smuzhiyun pinctrl-0 = <&i2c3_pins>; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun/* Needed to power the DPI pins */ 98*4882a593Smuzhiyun&vpll2 { 99*4882a593Smuzhiyun regulator-always-on; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&dss { 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun pinctrl-names = "default"; 106*4882a593Smuzhiyun pinctrl-0 = <&dss_dpi_pins>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun port { 109*4882a593Smuzhiyun dpi_out: endpoint { 110*4882a593Smuzhiyun remote-endpoint = <&lcd_in>; 111*4882a593Smuzhiyun data-lines = <24>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun/ { 117*4882a593Smuzhiyun aliases { 118*4882a593Smuzhiyun display0 = &lcd0; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun lcd0: display { 122*4882a593Smuzhiyun compatible = "panel-dpi"; 123*4882a593Smuzhiyun label = "lcd"; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun pinctrl-names = "default"; 126*4882a593Smuzhiyun pinctrl-0 = <<e430_pins>; 127*4882a593Smuzhiyun enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun port { 130*4882a593Smuzhiyun lcd_in: endpoint { 131*4882a593Smuzhiyun remote-endpoint = <&dpi_out>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun panel-timing { 136*4882a593Smuzhiyun clock-frequency = <31250000>; 137*4882a593Smuzhiyun hactive = <800>; 138*4882a593Smuzhiyun vactive = <480>; 139*4882a593Smuzhiyun hfront-porch = <40>; 140*4882a593Smuzhiyun hback-porch = <86>; 141*4882a593Smuzhiyun hsync-len = <1>; 142*4882a593Smuzhiyun vback-porch = <30>; 143*4882a593Smuzhiyun vfront-porch = <13>; 144*4882a593Smuzhiyun vsync-len = <3>; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun hsync-active = <0>; 147*4882a593Smuzhiyun vsync-active = <0>; 148*4882a593Smuzhiyun de-active = <1>; 149*4882a593Smuzhiyun pixelclk-active = <1>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun backlight { 154*4882a593Smuzhiyun compatible = "gpio-backlight"; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun pinctrl-names = "default"; 157*4882a593Smuzhiyun pinctrl-0 = <&backlight_pins>; 158*4882a593Smuzhiyun gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun default-on; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun}; 163