1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "omap34xx.dtsi" 8*4882a593Smuzhiyun#include "omap3-evm-common.dtsi" 9*4882a593Smuzhiyun#include "omap3-evm-processor-common.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "TI OMAP35XX EVM (TMDSEVM3530)"; 13*4882a593Smuzhiyun compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; 14*4882a593Smuzhiyun}; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun&omap3_pmx_core2 { 17*4882a593Smuzhiyun pinctrl-names = "default"; 18*4882a593Smuzhiyun pinctrl-0 = <&hsusb2_2_pins>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun ehci_phy_pins: pinmux_ehci_phy_pins { 21*4882a593Smuzhiyun pinctrl-single,pins = < 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* EHCI PHY reset GPIO etk_d7.gpio_21 */ 24*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* EHCI VBUS etk_d8.gpio_22 */ 27*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) 28*4882a593Smuzhiyun >; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Used by OHCI and EHCI. OHCI won't work without external phy */ 32*4882a593Smuzhiyun hsusb2_2_pins: pinmux_hsusb2_2_pins { 33*4882a593Smuzhiyun pinctrl-single,pins = < 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* etk_d10.hsusb2_clk */ 36*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* etk_d11.hsusb2_stp */ 39*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* etk_d12.hsusb2_dir */ 42*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* etk_d13.hsusb2_nxt */ 45*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* etk_d14.hsusb2_data0 */ 48*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* etk_d15.hsusb2_data1 */ 51*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) 52*4882a593Smuzhiyun >; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&gpmc { 57*4882a593Smuzhiyun nand@0,0 { 58*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 59*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 60*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 61*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 62*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 63*4882a593Smuzhiyun linux,mtd-name= "micron,mt29f2g16abdhc"; 64*4882a593Smuzhiyun nand-bus-width = <16>; 65*4882a593Smuzhiyun gpmc,device-width = <2>; 66*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 69*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 70*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 71*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 72*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 73*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 74*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 75*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 76*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 77*4882a593Smuzhiyun gpmc,access-ns = <64>; 78*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 79*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 80*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 81*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #address-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <1>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87