1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2019 André Hentschel <nerv@dawncrow.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dm3725.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Amazon Echo (first generation)"; 13*4882a593Smuzhiyun compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpus { 16*4882a593Smuzhiyun cpu@0 { 17*4882a593Smuzhiyun cpu0-supply = <&vdd1_reg>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@80000000 { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun reg = <0x80000000 0xc600000>; /* 198 MB */ 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun vcc5v: fixedregulator0 { 27*4882a593Smuzhiyun compatible = "regulator-fixed"; 28*4882a593Smuzhiyun regulator-name = "vcc5v"; 29*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 30*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 31*4882a593Smuzhiyun regulator-boot-on; 32*4882a593Smuzhiyun regulator-always-on; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun vcc3v3: fixedregulator1 { 36*4882a593Smuzhiyun compatible = "regulator-fixed"; 37*4882a593Smuzhiyun regulator-name = "vcc3v3"; 38*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 39*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 40*4882a593Smuzhiyun regulator-boot-on; 41*4882a593Smuzhiyun regulator-always-on; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun vcc1v8: fixedregulator2 { 45*4882a593Smuzhiyun compatible = "regulator-fixed"; 46*4882a593Smuzhiyun regulator-name = "vcc1v8"; 47*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 48*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 49*4882a593Smuzhiyun regulator-boot-on; 50*4882a593Smuzhiyun regulator-always-on; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 54*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 55*4882a593Smuzhiyun reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; 56*4882a593Smuzhiyun post-power-on-delay-ms = <40>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun gpio-keys { 60*4882a593Smuzhiyun compatible = "gpio-keys"; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun pinctrl-names = "default"; 63*4882a593Smuzhiyun pinctrl-0 = <&button_pins>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun mute-button { 66*4882a593Smuzhiyun label = "mute"; 67*4882a593Smuzhiyun linux,code = <KEY_MUTE>; 68*4882a593Smuzhiyun gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */ 69*4882a593Smuzhiyun wakeup-source; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun help-button { 73*4882a593Smuzhiyun label = "help"; 74*4882a593Smuzhiyun linux,code = <KEY_HELP>; 75*4882a593Smuzhiyun gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */ 76*4882a593Smuzhiyun wakeup-source; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun rotary: rotary-encoder { 81*4882a593Smuzhiyun compatible = "rotary-encoder"; 82*4882a593Smuzhiyun gpios = < 83*4882a593Smuzhiyun &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */ 84*4882a593Smuzhiyun &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */ 85*4882a593Smuzhiyun >; 86*4882a593Smuzhiyun linux,axis = <REL_X>; 87*4882a593Smuzhiyun rotary-encoder,relative-axis; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&i2c1 { 92*4882a593Smuzhiyun clock-frequency = <400000>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun tps: tps@2d { 95*4882a593Smuzhiyun reg = <0x2d>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&i2c2 { 100*4882a593Smuzhiyun clock-frequency = <400000>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun lp5523A: lp5523A@32 { 103*4882a593Smuzhiyun compatible = "national,lp5523"; 104*4882a593Smuzhiyun label = "q1"; 105*4882a593Smuzhiyun reg = <0x32>; 106*4882a593Smuzhiyun clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ 107*4882a593Smuzhiyun enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun chan0 { 110*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 111*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun chan1 { 114*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 115*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun chan2 { 118*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 119*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun chan3 { 122*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 123*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun chan4 { 126*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 127*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun chan5 { 130*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 131*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun chan6 { 134*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 135*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun chan7 { 138*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 139*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun chan8 { 142*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 143*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun lp5523B: lp5523B@33 { 148*4882a593Smuzhiyun compatible = "national,lp5523"; 149*4882a593Smuzhiyun label = "q3"; 150*4882a593Smuzhiyun reg = <0x33>; 151*4882a593Smuzhiyun clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun chan0 { 154*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 155*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun chan1 { 158*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 159*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun chan2 { 162*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 163*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun chan3 { 166*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 167*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun chan4 { 170*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 171*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun chan5 { 174*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 175*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun chan6 { 178*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 179*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun chan7 { 182*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 183*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun chan8 { 186*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 187*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun lp5523C: lp5523C@34 { 192*4882a593Smuzhiyun compatible = "national,lp5523"; 193*4882a593Smuzhiyun label = "q4"; 194*4882a593Smuzhiyun reg = <0x34>; 195*4882a593Smuzhiyun clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun chan0 { 198*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 199*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun chan1 { 202*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 203*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun chan2 { 206*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 207*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun chan3 { 210*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 211*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun chan4 { 214*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 215*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun chan5 { 218*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 219*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun chan6 { 222*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 223*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun chan7 { 226*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 227*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun chan8 { 230*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 231*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun lp5523D: lp552D@35 { 236*4882a593Smuzhiyun compatible = "national,lp5523"; 237*4882a593Smuzhiyun label = "q2"; 238*4882a593Smuzhiyun reg = <0x35>; 239*4882a593Smuzhiyun clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun chan0 { 242*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 243*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun chan1 { 246*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 247*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun chan2 { 250*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 251*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun chan3 { 254*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 255*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun chan4 { 258*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 259*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun chan5 { 262*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 263*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun chan6 { 266*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 267*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun chan7 { 270*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 271*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun chan8 { 274*4882a593Smuzhiyun led-cur = /bits/ 8 <12>; 275*4882a593Smuzhiyun max-cur = /bits/ 8 <15>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun}; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun#include "tps65910.dtsi" 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun&omap3_pmx_core { 283*4882a593Smuzhiyun tps_pins: pinmux_tps_pins { 284*4882a593Smuzhiyun pinctrl-single,pins = < 285*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ 286*4882a593Smuzhiyun >; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun button_pins: pinmux_button_pins { 290*4882a593Smuzhiyun pinctrl-single,pins = < 291*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ 292*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ 293*4882a593Smuzhiyun >; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 297*4882a593Smuzhiyun pinctrl-single,pins = < 298*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 299*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 300*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 301*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 302*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 303*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 304*4882a593Smuzhiyun >; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun mmc2_pins: pinmux_mmc2_pins { 308*4882a593Smuzhiyun pinctrl-single,pins = < 309*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 310*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 311*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 312*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 313*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 314*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 315*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ 316*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ 317*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ 318*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ 319*4882a593Smuzhiyun >; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun}; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun&omap3_pmx_core2 { 324*4882a593Smuzhiyun mmc3_pins: pinmux_mmc3_pins { 325*4882a593Smuzhiyun pinctrl-single,pins = < 326*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ 327*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ 328*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ 329*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ 330*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ 331*4882a593Smuzhiyun OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ 332*4882a593Smuzhiyun >; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&mmc1 { 337*4882a593Smuzhiyun status = "okay"; 338*4882a593Smuzhiyun bus-width = <4>; 339*4882a593Smuzhiyun pinctrl-names = "default"; 340*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 341*4882a593Smuzhiyun vmmc-supply = <&vmmc_reg>; 342*4882a593Smuzhiyun}; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun&mmc2 { 345*4882a593Smuzhiyun status = "okay"; 346*4882a593Smuzhiyun bus-width = <8>; 347*4882a593Smuzhiyun pinctrl-names = "default"; 348*4882a593Smuzhiyun pinctrl-0 = <&mmc2_pins>; 349*4882a593Smuzhiyun vmmc-supply = <&vmmc_reg>; 350*4882a593Smuzhiyun}; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun&mmc3 { 353*4882a593Smuzhiyun status = "okay"; 354*4882a593Smuzhiyun bus-width = <4>; 355*4882a593Smuzhiyun pinctrl-names = "default"; 356*4882a593Smuzhiyun pinctrl-0 = <&mmc3_pins>; 357*4882a593Smuzhiyun non-removable; 358*4882a593Smuzhiyun disable-wp; 359*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 360*4882a593Smuzhiyun vmmc-supply = <&vcc3v3>; 361*4882a593Smuzhiyun vqmmc-supply = <&vcc1v8>; 362*4882a593Smuzhiyun}; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun&tps { 365*4882a593Smuzhiyun pinctrl-names = "default"; 366*4882a593Smuzhiyun pinctrl-0 = <&tps_pins>; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 369*4882a593Smuzhiyun interrupt-parent = <&intc>; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun ti,en-ck32k-xtal; 372*4882a593Smuzhiyun ti,system-power-controller; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun vcc1-supply = <&vcc5v>; 375*4882a593Smuzhiyun vcc2-supply = <&vcc5v>; 376*4882a593Smuzhiyun vcc3-supply = <&vcc5v>; 377*4882a593Smuzhiyun vcc4-supply = <&vcc5v>; 378*4882a593Smuzhiyun vcc5-supply = <&vcc5v>; 379*4882a593Smuzhiyun vcc6-supply = <&vcc5v>; 380*4882a593Smuzhiyun vcc7-supply = <&vcc5v>; 381*4882a593Smuzhiyun vccio-supply = <&vcc5v>; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun regulators { 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun vio_reg: regulator@1 { 386*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 387*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 388*4882a593Smuzhiyun regulator-always-on; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun vdd1_reg: regulator@2 { 392*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 393*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 394*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 395*4882a593Smuzhiyun regulator-boot-on; 396*4882a593Smuzhiyun regulator-always-on; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun vdd2_reg: regulator@3 { 400*4882a593Smuzhiyun regulator-name = "vdd_dsp"; 401*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 402*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 403*4882a593Smuzhiyun regulator-always-on; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun vdd3_reg: regulator@4 { 407*4882a593Smuzhiyun regulator-name = "vdd_core"; 408*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 409*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 410*4882a593Smuzhiyun regulator-always-on; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun vdig1_reg: regulator@5 { 414*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 415*4882a593Smuzhiyun regulator-max-microvolt = <2700000>; 416*4882a593Smuzhiyun regulator-always-on; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun vdig2_reg: regulator@6 { 420*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 421*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 422*4882a593Smuzhiyun regulator-always-on; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun vpll_reg: regulator@7 { 426*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 427*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 428*4882a593Smuzhiyun regulator-always-on; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun vdac_reg: regulator@8 { 432*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 433*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 434*4882a593Smuzhiyun regulator-always-on; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun vaux1_reg: regulator@9 { 438*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 439*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 440*4882a593Smuzhiyun regulator-always-on; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun vaux2_reg: regulator@10 { 444*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 445*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 446*4882a593Smuzhiyun regulator-always-on; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun vaux33_reg: regulator@11 { 450*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 451*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 452*4882a593Smuzhiyun regulator-always-on; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun vmmc_reg: regulator@12 { 456*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 457*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 458*4882a593Smuzhiyun regulator-always-on; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun}; 462