xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/omap3-devkit8000-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Author: Anil Kumar <anilk4.v@gmail.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "omap34xx.dtsi"
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	memory@80000000 {
11*4882a593Smuzhiyun		device_type = "memory";
12*4882a593Smuzhiyun		reg = <0x80000000 0x10000000>;	/* 256 MB */
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	leds {
16*4882a593Smuzhiyun		compatible = "gpio-leds";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun		heartbeat {
19*4882a593Smuzhiyun			label = "devkit8000::led1";
20*4882a593Smuzhiyun			gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;	/* 186 -> LED1 */
21*4882a593Smuzhiyun			default-state = "on";
22*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
23*4882a593Smuzhiyun		};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun		mmc {
26*4882a593Smuzhiyun			label = "devkit8000::led2";
27*4882a593Smuzhiyun			gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;	/* 163 -> LED2 */
28*4882a593Smuzhiyun			default-state = "on";
29*4882a593Smuzhiyun			linux,default-trigger = "none";
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		usr {
33*4882a593Smuzhiyun			label = "devkit8000::led3";
34*4882a593Smuzhiyun			gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;	/* 164 -> LED3 */
35*4882a593Smuzhiyun			default-state = "on";
36*4882a593Smuzhiyun			linux,default-trigger = "usr";
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		pmu_stat {
40*4882a593Smuzhiyun			label = "devkit8000::pmu_stat";
41*4882a593Smuzhiyun			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	sound {
46*4882a593Smuzhiyun		compatible = "ti,omap-twl4030";
47*4882a593Smuzhiyun		ti,model = "devkit8000";
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		ti,mcbsp = <&mcbsp2>;
50*4882a593Smuzhiyun		ti,audio-routing =
51*4882a593Smuzhiyun			"Ext Spk", "PREDRIVEL",
52*4882a593Smuzhiyun			"Ext Spk", "PREDRIVER",
53*4882a593Smuzhiyun			"MAINMIC", "Main Mic",
54*4882a593Smuzhiyun			"Main Mic", "Mic Bias 1";
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	gpio_keys {
58*4882a593Smuzhiyun		compatible = "gpio-keys";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		user {
61*4882a593Smuzhiyun			label = "user";
62*4882a593Smuzhiyun			gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
63*4882a593Smuzhiyun			linux,code = <BTN_EXTRA>;
64*4882a593Smuzhiyun			wakeup-source;
65*4882a593Smuzhiyun		};
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	tfp410: encoder0 {
69*4882a593Smuzhiyun		compatible = "ti,tfp410";
70*4882a593Smuzhiyun		powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		ports {
73*4882a593Smuzhiyun			#address-cells = <1>;
74*4882a593Smuzhiyun			#size-cells = <0>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun			port@0 {
77*4882a593Smuzhiyun				reg = <0>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun				tfp410_in: endpoint {
80*4882a593Smuzhiyun					remote-endpoint = <&dpi_dvi_out>;
81*4882a593Smuzhiyun				};
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun			port@1 {
85*4882a593Smuzhiyun				reg = <1>;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun				tfp410_out: endpoint {
88*4882a593Smuzhiyun					remote-endpoint = <&dvi_connector_in>;
89*4882a593Smuzhiyun				};
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	dvi0: connector0 {
95*4882a593Smuzhiyun		compatible = "dvi-connector";
96*4882a593Smuzhiyun		label = "dvi";
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		digital;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		ddc-i2c-bus = <&i2c2>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		port {
103*4882a593Smuzhiyun			dvi_connector_in: endpoint {
104*4882a593Smuzhiyun				remote-endpoint = <&tfp410_out>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	tv0: connector1 {
110*4882a593Smuzhiyun		compatible = "svideo-connector";
111*4882a593Smuzhiyun		label = "tv";
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun		port {
114*4882a593Smuzhiyun			tv_connector_in: endpoint {
115*4882a593Smuzhiyun				remote-endpoint = <&venc_out>;
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&i2c1 {
122*4882a593Smuzhiyun	clock-frequency = <2600000>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	twl: twl@48 {
125*4882a593Smuzhiyun		reg = <0x48>;
126*4882a593Smuzhiyun		interrupts = <7>;	/* SYS_NIRQ cascaded to intc */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		twl_audio: audio {
129*4882a593Smuzhiyun			compatible = "ti,twl4030-audio";
130*4882a593Smuzhiyun			codec {
131*4882a593Smuzhiyun			};
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&i2c2 {
137*4882a593Smuzhiyun	clock-frequency = <400000>;
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&i2c3 {
141*4882a593Smuzhiyun	status = "disabled";
142*4882a593Smuzhiyun};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun#include "twl4030.dtsi"
145*4882a593Smuzhiyun#include "twl4030_omap3.dtsi"
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun&mmc1 {
148*4882a593Smuzhiyun	vmmc-supply = <&vmmc1>;
149*4882a593Smuzhiyun	vqmmc-supply = <&vsim>;
150*4882a593Smuzhiyun	bus-width = <8>;
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&mmc2 {
154*4882a593Smuzhiyun	status = "disabled";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&mmc3 {
158*4882a593Smuzhiyun	status = "disabled";
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun/* Unusable as clockevent because if unreliable oscillator, allow to idle */
162*4882a593Smuzhiyun&timer1_target {
163*4882a593Smuzhiyun	/delete-property/ti,no-reset-on-init;
164*4882a593Smuzhiyun	/delete-property/ti,no-idle;
165*4882a593Smuzhiyun	timer@0 {
166*4882a593Smuzhiyun		/delete-property/ti,timer-alwon;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun/* Preferred timer for clockevent */
171*4882a593Smuzhiyun&timer12_target {
172*4882a593Smuzhiyun	ti,no-reset-on-init;
173*4882a593Smuzhiyun	ti,no-idle;
174*4882a593Smuzhiyun	timer@0 {
175*4882a593Smuzhiyun		/* Always clocked by secure_32k_fck */
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&twl_gpio {
180*4882a593Smuzhiyun	ti,use-leds;
181*4882a593Smuzhiyun	/*
182*4882a593Smuzhiyun	 * pulldowns:
183*4882a593Smuzhiyun	 * BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
184*4882a593Smuzhiyun	 * BIT(15), BIT(16), BIT(17)
185*4882a593Smuzhiyun	 */
186*4882a593Smuzhiyun	ti,pulldowns = <0x03a1c6>;
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun&twl_keypad {
190*4882a593Smuzhiyun	linux,keymap = <MATRIX_KEY(0, 0, KEY_1)
191*4882a593Smuzhiyun			MATRIX_KEY(1, 0, KEY_2)
192*4882a593Smuzhiyun			MATRIX_KEY(2, 0, KEY_3)
193*4882a593Smuzhiyun			MATRIX_KEY(0, 1, KEY_4)
194*4882a593Smuzhiyun			MATRIX_KEY(1, 1, KEY_5)
195*4882a593Smuzhiyun			MATRIX_KEY(2, 1, KEY_6)
196*4882a593Smuzhiyun			MATRIX_KEY(3, 1, KEY_F5)
197*4882a593Smuzhiyun			MATRIX_KEY(0, 2, KEY_7)
198*4882a593Smuzhiyun			MATRIX_KEY(1, 2, KEY_8)
199*4882a593Smuzhiyun			MATRIX_KEY(2, 2, KEY_9)
200*4882a593Smuzhiyun			MATRIX_KEY(3, 2, KEY_F6)
201*4882a593Smuzhiyun			MATRIX_KEY(0, 3, KEY_F7)
202*4882a593Smuzhiyun			MATRIX_KEY(1, 3, KEY_0)
203*4882a593Smuzhiyun			MATRIX_KEY(2, 3, KEY_F8)
204*4882a593Smuzhiyun			MATRIX_KEY(4, 5, KEY_RESERVED)
205*4882a593Smuzhiyun			MATRIX_KEY(4, 4, KEY_VOLUMEUP)
206*4882a593Smuzhiyun			MATRIX_KEY(5, 5, KEY_VOLUMEDOWN)
207*4882a593Smuzhiyun			>;
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&wdt2 {
211*4882a593Smuzhiyun	status = "disabled";
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&mcbsp2 {
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&gpmc {
219*4882a593Smuzhiyun	ranges = <0 0 0x30000000 0x1000000	/* CS0: 16MB for NAND */
220*4882a593Smuzhiyun		  6 0 0x2c000000 0x1000000>;	/* CS6: 16MB for DM9000 */
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun	nand@0,0 {
223*4882a593Smuzhiyun		compatible = "ti,omap2-nand";
224*4882a593Smuzhiyun		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
225*4882a593Smuzhiyun		interrupt-parent = <&gpmc>;
226*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
227*4882a593Smuzhiyun			     <1 IRQ_TYPE_NONE>;	/* termcount */
228*4882a593Smuzhiyun		nand-bus-width = <16>;
229*4882a593Smuzhiyun		gpmc,device-width = <2>;
230*4882a593Smuzhiyun		ti,nand-ecc-opt = "sw";
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
233*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
234*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
235*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
236*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
237*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
238*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
239*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
240*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
241*4882a593Smuzhiyun		gpmc,access-ns = <64>;
242*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
243*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
244*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
245*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun		#address-cells = <1>;
248*4882a593Smuzhiyun		#size-cells = <1>;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		x-loader@0 {
251*4882a593Smuzhiyun			label = "X-Loader";
252*4882a593Smuzhiyun			reg = <0 0x80000>;
253*4882a593Smuzhiyun		};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		bootloaders@80000 {
256*4882a593Smuzhiyun			label = "U-Boot";
257*4882a593Smuzhiyun			reg = <0x80000 0x1e0000>;
258*4882a593Smuzhiyun		};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun		bootloaders_env@260000 {
261*4882a593Smuzhiyun			label = "U-Boot Env";
262*4882a593Smuzhiyun			reg = <0x260000 0x20000>;
263*4882a593Smuzhiyun		};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun		kernel@280000 {
266*4882a593Smuzhiyun			label = "Kernel";
267*4882a593Smuzhiyun			reg = <0x280000 0x400000>;
268*4882a593Smuzhiyun		};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun		filesystem@680000 {
271*4882a593Smuzhiyun			label = "File System";
272*4882a593Smuzhiyun			reg = <0x680000 0xf980000>;
273*4882a593Smuzhiyun		};
274*4882a593Smuzhiyun	};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun	ethernet@6,0 {
277*4882a593Smuzhiyun		compatible = "davicom,dm9000";
278*4882a593Smuzhiyun		reg =  <6 0x000 2
279*4882a593Smuzhiyun			6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */
280*4882a593Smuzhiyun		bank-width = <2>;
281*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
282*4882a593Smuzhiyun		interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
283*4882a593Smuzhiyun		davicom,no-eeprom;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun		gpmc,mux-add-data = <0>;
286*4882a593Smuzhiyun		gpmc,device-width = <1>;
287*4882a593Smuzhiyun		gpmc,wait-pin = <0>;
288*4882a593Smuzhiyun		gpmc,cycle2cycle-samecsen = <1>;
289*4882a593Smuzhiyun		gpmc,cycle2cycle-diffcsen = <1>;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun		gpmc,cs-on-ns = <6>;
292*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <180>;
293*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <180>;
294*4882a593Smuzhiyun		gpmc,adv-on-ns = <0>;
295*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <18>;
296*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <48>;
297*4882a593Smuzhiyun		gpmc,oe-on-ns = <54>;
298*4882a593Smuzhiyun		gpmc,oe-off-ns = <168>;
299*4882a593Smuzhiyun		gpmc,we-on-ns = <54>;
300*4882a593Smuzhiyun		gpmc,we-off-ns = <168>;
301*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <186>;
302*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <186>;
303*4882a593Smuzhiyun		gpmc,access-ns = <144>;
304*4882a593Smuzhiyun		gpmc,page-burst-access-ns = <24>;
305*4882a593Smuzhiyun		gpmc,bus-turnaround-ns = <90>;
306*4882a593Smuzhiyun		gpmc,cycle2cycle-delay-ns = <90>;
307*4882a593Smuzhiyun		gpmc,wait-monitoring-ns = <0>;
308*4882a593Smuzhiyun		gpmc,clk-activation-ns = <0>;
309*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
310*4882a593Smuzhiyun		gpmc,wr-access-ns = <0>;
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&omap3_pmx_core {
315*4882a593Smuzhiyun	dss_dpi_pins: pinmux_dss_dpi_pins {
316*4882a593Smuzhiyun		pinctrl-single,pins = <
317*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)	/* dss_pclk.dss_pclk */
318*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)	/* dss_hsync.dss_hsync */
319*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)	/* dss_vsync.dss_vsync */
320*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)	/* dss_acbias.dss_acbias */
321*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)	/* dss_data0.dss_data0 */
322*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)	/* dss_data1.dss_data1 */
323*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)	/* dss_data2.dss_data2 */
324*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)	/* dss_data3.dss_data3 */
325*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)	/* dss_data4.dss_data4 */
326*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)	/* dss_data5.dss_data5 */
327*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)	/* dss_data6.dss_data6 */
328*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)	/* dss_data7.dss_data7 */
329*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)	/* dss_data8.dss_data8 */
330*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)	/* dss_data9.dss_data9 */
331*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)	/* dss_data10.dss_data10 */
332*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)	/* dss_data11.dss_data11 */
333*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)	/* dss_data12.dss_data12 */
334*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)	/* dss_data13.dss_data13 */
335*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)	/* dss_data14.dss_data14 */
336*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)	/* dss_data15.dss_data15 */
337*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)	/* dss_data16.dss_data16 */
338*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)	/* dss_data17.dss_data17 */
339*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)	/* dss_data18.dss_data18 */
340*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)	/* dss_data19.dss_data19 */
341*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)	/* dss_data20.dss_data20 */
342*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)	/* dss_data21.dss_data21 */
343*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)	/* dss_data22.dss_data22 */
344*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)	/* dss_data23.dss_data23 */
345*4882a593Smuzhiyun		>;
346*4882a593Smuzhiyun	};
347*4882a593Smuzhiyun};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun&vpll1 {
350*4882a593Smuzhiyun	/* Needed for DSS */
351*4882a593Smuzhiyun	regulator-name = "vdds_dsi";
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun	regulator-min-microvolt = <1800000>;
354*4882a593Smuzhiyun	regulator-max-microvolt = <1800000>;
355*4882a593Smuzhiyun};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun&dss {
358*4882a593Smuzhiyun	status = "okay";
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun	pinctrl-names = "default";
361*4882a593Smuzhiyun	pinctrl-0 = <&dss_dpi_pins>;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun	vdds_dsi-supply = <&vpll1>;
364*4882a593Smuzhiyun	vdda_dac-supply = <&vdac>;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun	port {
367*4882a593Smuzhiyun		#address-cells = <1>;
368*4882a593Smuzhiyun		#size-cells = <0>;
369*4882a593Smuzhiyun		dpi_dvi_out: endpoint@0 {
370*4882a593Smuzhiyun			reg = <0>;
371*4882a593Smuzhiyun			remote-endpoint = <&tfp410_in>;
372*4882a593Smuzhiyun			data-lines = <24>;
373*4882a593Smuzhiyun		};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun		endpoint@1 {
376*4882a593Smuzhiyun			reg = <1>;
377*4882a593Smuzhiyun		};
378*4882a593Smuzhiyun	};
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun&venc {
382*4882a593Smuzhiyun	status = "okay";
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun	vdda-supply = <&vdac>;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun	port {
387*4882a593Smuzhiyun		venc_out: endpoint {
388*4882a593Smuzhiyun			remote-endpoint = <&tv_connector_in>;
389*4882a593Smuzhiyun			ti,channels = <2>;
390*4882a593Smuzhiyun		};
391*4882a593Smuzhiyun	};
392*4882a593Smuzhiyun};
393