1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "omap34xx.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "TI OMAP3 BeagleBoard"; 11*4882a593Smuzhiyun compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun cpu@0 { 15*4882a593Smuzhiyun cpu0-supply = <&vcc>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@80000000 { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun aliases { 25*4882a593Smuzhiyun display0 = &dvi0; 26*4882a593Smuzhiyun display1 = &tv0; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun leds { 30*4882a593Smuzhiyun compatible = "gpio-leds"; 31*4882a593Smuzhiyun pmu_stat { 32*4882a593Smuzhiyun label = "beagleboard::pmu_stat"; 33*4882a593Smuzhiyun gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun heartbeat { 37*4882a593Smuzhiyun label = "beagleboard::usr0"; 38*4882a593Smuzhiyun gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ 39*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun mmc { 43*4882a593Smuzhiyun label = "beagleboard::usr1"; 44*4882a593Smuzhiyun gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ 45*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* HS USB Port 2 Power */ 50*4882a593Smuzhiyun hsusb2_power: hsusb2_power_reg { 51*4882a593Smuzhiyun compatible = "regulator-fixed"; 52*4882a593Smuzhiyun regulator-name = "hsusb2_vbus"; 53*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 54*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 55*4882a593Smuzhiyun gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ 56*4882a593Smuzhiyun startup-delay-us = <70000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* HS USB Host PHY on PORT 2 */ 60*4882a593Smuzhiyun hsusb2_phy: hsusb2_phy { 61*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 62*4882a593Smuzhiyun reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ 63*4882a593Smuzhiyun vcc-supply = <&hsusb2_power>; 64*4882a593Smuzhiyun #phy-cells = <0>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun sound { 68*4882a593Smuzhiyun compatible = "ti,omap-twl4030"; 69*4882a593Smuzhiyun ti,model = "omap3beagle"; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun ti,mcbsp = <&mcbsp2>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun gpio_keys { 75*4882a593Smuzhiyun compatible = "gpio-keys"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun user { 78*4882a593Smuzhiyun label = "user"; 79*4882a593Smuzhiyun gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 80*4882a593Smuzhiyun linux,code = <0x114>; 81*4882a593Smuzhiyun wakeup-source; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun tfp410: encoder0 { 87*4882a593Smuzhiyun compatible = "ti,tfp410"; 88*4882a593Smuzhiyun powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun pinctrl-names = "default"; 91*4882a593Smuzhiyun pinctrl-0 = <&tfp410_pins>; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun ports { 94*4882a593Smuzhiyun #address-cells = <1>; 95*4882a593Smuzhiyun #size-cells = <0>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun port@0 { 98*4882a593Smuzhiyun reg = <0>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun tfp410_in: endpoint { 101*4882a593Smuzhiyun remote-endpoint = <&dpi_out>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun port@1 { 106*4882a593Smuzhiyun reg = <1>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun tfp410_out: endpoint { 109*4882a593Smuzhiyun remote-endpoint = <&dvi_connector_in>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun dvi0: connector0 { 116*4882a593Smuzhiyun compatible = "dvi-connector"; 117*4882a593Smuzhiyun label = "dvi"; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun digital; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun ddc-i2c-bus = <&i2c3>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun port { 124*4882a593Smuzhiyun dvi_connector_in: endpoint { 125*4882a593Smuzhiyun remote-endpoint = <&tfp410_out>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun tv0: connector1 { 131*4882a593Smuzhiyun compatible = "svideo-connector"; 132*4882a593Smuzhiyun label = "tv"; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun port { 135*4882a593Smuzhiyun tv_connector_in: endpoint { 136*4882a593Smuzhiyun remote-endpoint = <&venc_out>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun etb@540000000 { 142*4882a593Smuzhiyun compatible = "arm,coresight-etb10", "arm,primecell"; 143*4882a593Smuzhiyun reg = <0x5401b000 0x1000>; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun clocks = <&emu_src_ck>; 146*4882a593Smuzhiyun clock-names = "apb_pclk"; 147*4882a593Smuzhiyun in-ports { 148*4882a593Smuzhiyun port { 149*4882a593Smuzhiyun etb_in: endpoint { 150*4882a593Smuzhiyun remote-endpoint = <&etm_out>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun etm@54010000 { 157*4882a593Smuzhiyun compatible = "arm,coresight-etm3x", "arm,primecell"; 158*4882a593Smuzhiyun reg = <0x54010000 0x1000>; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun clocks = <&emu_src_ck>; 161*4882a593Smuzhiyun clock-names = "apb_pclk"; 162*4882a593Smuzhiyun out-ports { 163*4882a593Smuzhiyun port { 164*4882a593Smuzhiyun etm_out: endpoint { 165*4882a593Smuzhiyun remote-endpoint = <&etb_in>; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&omap3_pmx_wkup { 173*4882a593Smuzhiyun gpio1_pins: pinmux_gpio1_pins { 174*4882a593Smuzhiyun pinctrl-single,pins = < 175*4882a593Smuzhiyun OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ 176*4882a593Smuzhiyun >; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun&omap3_pmx_core { 181*4882a593Smuzhiyun pinctrl-names = "default"; 182*4882a593Smuzhiyun pinctrl-0 = < 183*4882a593Smuzhiyun &hsusb2_pins 184*4882a593Smuzhiyun >; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun hsusb2_pins: pinmux_hsusb2_pins { 187*4882a593Smuzhiyun pinctrl-single,pins = < 188*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ 189*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ 190*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ 191*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ 192*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ 193*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ 194*4882a593Smuzhiyun >; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun uart3_pins: pinmux_uart3_pins { 198*4882a593Smuzhiyun pinctrl-single,pins = < 199*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 200*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 201*4882a593Smuzhiyun >; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun tfp410_pins: pinmux_tfp410_pins { 205*4882a593Smuzhiyun pinctrl-single,pins = < 206*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 207*4882a593Smuzhiyun >; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun dss_dpi_pins: pinmux_dss_dpi_pins { 211*4882a593Smuzhiyun pinctrl-single,pins = < 212*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 213*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 214*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 215*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 216*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 217*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 218*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 219*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 220*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 221*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 222*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 223*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 224*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 225*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 226*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 227*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 228*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 229*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 230*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 231*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 232*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 233*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 234*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 235*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 236*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 237*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 238*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 239*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 240*4882a593Smuzhiyun >; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&omap3_pmx_core2 { 245*4882a593Smuzhiyun pinctrl-names = "default"; 246*4882a593Smuzhiyun pinctrl-0 = < 247*4882a593Smuzhiyun &hsusb2_2_pins 248*4882a593Smuzhiyun >; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun hsusb2_2_pins: pinmux_hsusb2_2_pins { 251*4882a593Smuzhiyun pinctrl-single,pins = < 252*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ 253*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ 254*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ 255*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ 256*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ 257*4882a593Smuzhiyun OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ 258*4882a593Smuzhiyun >; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&i2c1 { 263*4882a593Smuzhiyun clock-frequency = <2600000>; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun twl: twl@48 { 266*4882a593Smuzhiyun reg = <0x48>; 267*4882a593Smuzhiyun interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 268*4882a593Smuzhiyun interrupt-parent = <&intc>; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun twl_audio: audio { 271*4882a593Smuzhiyun compatible = "ti,twl4030-audio"; 272*4882a593Smuzhiyun codec { 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun#include "twl4030.dtsi" 279*4882a593Smuzhiyun#include "twl4030_omap3.dtsi" 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun&i2c3 { 282*4882a593Smuzhiyun clock-frequency = <100000>; 283*4882a593Smuzhiyun}; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun&mmc1 { 286*4882a593Smuzhiyun vmmc-supply = <&vmmc1>; 287*4882a593Smuzhiyun vqmmc-supply = <&vsim>; 288*4882a593Smuzhiyun bus-width = <8>; 289*4882a593Smuzhiyun}; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun&mmc2 { 292*4882a593Smuzhiyun status = "disabled"; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun&mmc3 { 296*4882a593Smuzhiyun status = "disabled"; 297*4882a593Smuzhiyun}; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun&usbhshost { 300*4882a593Smuzhiyun port2-mode = "ehci-phy"; 301*4882a593Smuzhiyun}; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun&usbhsehci { 304*4882a593Smuzhiyun phys = <0 &hsusb2_phy>; 305*4882a593Smuzhiyun}; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun&twl_gpio { 308*4882a593Smuzhiyun ti,use-leds; 309*4882a593Smuzhiyun /* pullups: BIT(1) */ 310*4882a593Smuzhiyun ti,pullups = <0x000002>; 311*4882a593Smuzhiyun /* 312*4882a593Smuzhiyun * pulldowns: 313*4882a593Smuzhiyun * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) 314*4882a593Smuzhiyun * BIT(15), BIT(16), BIT(17) 315*4882a593Smuzhiyun */ 316*4882a593Smuzhiyun ti,pulldowns = <0x03a1c4>; 317*4882a593Smuzhiyun}; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun&uart3 { 320*4882a593Smuzhiyun pinctrl-names = "default"; 321*4882a593Smuzhiyun pinctrl-0 = <&uart3_pins>; 322*4882a593Smuzhiyun interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 323*4882a593Smuzhiyun}; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun&gpio1 { 326*4882a593Smuzhiyun pinctrl-names = "default"; 327*4882a593Smuzhiyun pinctrl-0 = <&gpio1_pins>; 328*4882a593Smuzhiyun}; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun&usb_otg_hs { 331*4882a593Smuzhiyun interface-type = <0>; 332*4882a593Smuzhiyun usb-phy = <&usb2_phy>; 333*4882a593Smuzhiyun phys = <&usb2_phy>; 334*4882a593Smuzhiyun phy-names = "usb2-phy"; 335*4882a593Smuzhiyun mode = <3>; 336*4882a593Smuzhiyun power = <50>; 337*4882a593Smuzhiyun}; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun&vaux2 { 340*4882a593Smuzhiyun regulator-name = "vdd_ehci"; 341*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 342*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 343*4882a593Smuzhiyun regulator-always-on; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&mcbsp2 { 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun/* Needed to power the DPI pins */ 351*4882a593Smuzhiyun&vpll2 { 352*4882a593Smuzhiyun regulator-always-on; 353*4882a593Smuzhiyun}; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun&dss { 356*4882a593Smuzhiyun status = "okay"; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun pinctrl-names = "default"; 359*4882a593Smuzhiyun pinctrl-0 = <&dss_dpi_pins>; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun port { 362*4882a593Smuzhiyun dpi_out: endpoint { 363*4882a593Smuzhiyun remote-endpoint = <&tfp410_in>; 364*4882a593Smuzhiyun data-lines = <24>; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun}; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun&venc { 370*4882a593Smuzhiyun status = "okay"; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun vdda-supply = <&vdac>; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun port { 375*4882a593Smuzhiyun venc_out: endpoint { 376*4882a593Smuzhiyun remote-endpoint = <&tv_connector_in>; 377*4882a593Smuzhiyun ti,channels = <2>; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun}; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun&gpmc { 383*4882a593Smuzhiyun status = "okay"; 384*4882a593Smuzhiyun ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun /* Chip select 0 */ 387*4882a593Smuzhiyun nand@0,0 { 388*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 389*4882a593Smuzhiyun reg = <0 0 4>; /* NAND I/O window, 4 bytes */ 390*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 391*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 392*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 393*4882a593Smuzhiyun ti,nand-ecc-opt = "ham1"; 394*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 395*4882a593Smuzhiyun nand-bus-width = <16>; 396*4882a593Smuzhiyun #address-cells = <1>; 397*4882a593Smuzhiyun #size-cells = <1>; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun gpmc,device-width = <2>; 400*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 401*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <36>; 402*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <36>; 403*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 404*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <24>; 405*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <36>; 406*4882a593Smuzhiyun gpmc,oe-on-ns = <6>; 407*4882a593Smuzhiyun gpmc,oe-off-ns = <48>; 408*4882a593Smuzhiyun gpmc,we-on-ns = <6>; 409*4882a593Smuzhiyun gpmc,we-off-ns = <30>; 410*4882a593Smuzhiyun gpmc,rd-cycle-ns = <72>; 411*4882a593Smuzhiyun gpmc,wr-cycle-ns = <72>; 412*4882a593Smuzhiyun gpmc,access-ns = <54>; 413*4882a593Smuzhiyun gpmc,wr-access-ns = <30>; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun partition@0 { 416*4882a593Smuzhiyun label = "X-Loader"; 417*4882a593Smuzhiyun reg = <0 0x80000>; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun partition@80000 { 420*4882a593Smuzhiyun label = "U-Boot"; 421*4882a593Smuzhiyun reg = <0x80000 0x1e0000>; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun partition@1c0000 { 424*4882a593Smuzhiyun label = "U-Boot Env"; 425*4882a593Smuzhiyun reg = <0x260000 0x20000>; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun partition@280000 { 428*4882a593Smuzhiyun label = "Kernel"; 429*4882a593Smuzhiyun reg = <0x280000 0x400000>; 430*4882a593Smuzhiyun }; 431*4882a593Smuzhiyun partition@780000 { 432*4882a593Smuzhiyun label = "Filesystem"; 433*4882a593Smuzhiyun reg = <0x680000 0xf980000>; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun}; 437