1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree Source for OMAP243x SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License 7*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any 8*4882a593Smuzhiyun * kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "omap2.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun compatible = "ti,omap2430", "ti,omap2"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun ocp { 17*4882a593Smuzhiyun l4_wkup: l4_wkup@49000000 { 18*4882a593Smuzhiyun compatible = "ti,omap2-l4-wkup", "simple-bus"; 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <1>; 21*4882a593Smuzhiyun ranges = <0 0x49000000 0x31000>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun prcm: prcm@6000 { 24*4882a593Smuzhiyun compatible = "ti,omap2-prcm"; 25*4882a593Smuzhiyun reg = <0x6000 0x1000>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun prcm_clocks: clocks { 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun prcm_clockdomains: clockdomains { 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun scm: scm@2000 { 37*4882a593Smuzhiyun compatible = "ti,omap2-scm", "simple-bus"; 38*4882a593Smuzhiyun reg = <0x2000 0x1000>; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <1>; 41*4882a593Smuzhiyun #pinctrl-cells = <1>; 42*4882a593Smuzhiyun ranges = <0 0x2000 0x1000>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun omap2430_pmx: pinmux@30 { 45*4882a593Smuzhiyun compatible = "ti,omap2430-padconf", 46*4882a593Smuzhiyun "pinctrl-single"; 47*4882a593Smuzhiyun reg = <0x30 0x0154>; 48*4882a593Smuzhiyun #address-cells = <1>; 49*4882a593Smuzhiyun #size-cells = <0>; 50*4882a593Smuzhiyun #pinctrl-cells = <1>; 51*4882a593Smuzhiyun pinctrl-single,register-width = <8>; 52*4882a593Smuzhiyun pinctrl-single,function-mask = <0x3f>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun scm_conf: scm_conf@270 { 56*4882a593Smuzhiyun compatible = "syscon", 57*4882a593Smuzhiyun "simple-bus"; 58*4882a593Smuzhiyun reg = <0x270 0x240>; 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <1>; 61*4882a593Smuzhiyun ranges = <0 0x270 0x240>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun scm_clocks: clocks { 64*4882a593Smuzhiyun #address-cells = <1>; 65*4882a593Smuzhiyun #size-cells = <0>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun pbias_regulator: pbias_regulator@230 { 69*4882a593Smuzhiyun compatible = "ti,pbias-omap2", "ti,pbias-omap"; 70*4882a593Smuzhiyun reg = <0x230 0x4>; 71*4882a593Smuzhiyun syscon = <&scm_conf>; 72*4882a593Smuzhiyun pbias_mmc_reg: pbias_mmc_omap2430 { 73*4882a593Smuzhiyun regulator-name = "pbias_mmc_omap2430"; 74*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 75*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun scm_clockdomains: clockdomains { 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun target-module@20000 { 85*4882a593Smuzhiyun compatible = "ti,sysc-omap2", "ti,sysc"; 86*4882a593Smuzhiyun reg = <0x20000 0x4>, 87*4882a593Smuzhiyun <0x20004 0x4>; 88*4882a593Smuzhiyun reg-names = "rev", "sysc"; 89*4882a593Smuzhiyun ti,sysc-sidle = <SYSC_IDLE_FORCE>, 90*4882a593Smuzhiyun <SYSC_IDLE_NO>; 91*4882a593Smuzhiyun clocks = <&func_32k_ck>; 92*4882a593Smuzhiyun clock-names = "fck"; 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <1>; 95*4882a593Smuzhiyun ranges = <0x0 0x20000 0x1000>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun counter32k: counter@0 { 98*4882a593Smuzhiyun compatible = "ti,omap-counter32k"; 99*4882a593Smuzhiyun reg = <0 0x20>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun gpio1: gpio@4900c000 { 105*4882a593Smuzhiyun compatible = "ti,omap2-gpio"; 106*4882a593Smuzhiyun reg = <0x4900c000 0x200>; 107*4882a593Smuzhiyun interrupts = <29>; 108*4882a593Smuzhiyun ti,hwmods = "gpio1"; 109*4882a593Smuzhiyun ti,gpio-always-on; 110*4882a593Smuzhiyun #gpio-cells = <2>; 111*4882a593Smuzhiyun gpio-controller; 112*4882a593Smuzhiyun #interrupt-cells = <2>; 113*4882a593Smuzhiyun interrupt-controller; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun gpio2: gpio@4900e000 { 117*4882a593Smuzhiyun compatible = "ti,omap2-gpio"; 118*4882a593Smuzhiyun reg = <0x4900e000 0x200>; 119*4882a593Smuzhiyun interrupts = <30>; 120*4882a593Smuzhiyun ti,hwmods = "gpio2"; 121*4882a593Smuzhiyun ti,gpio-always-on; 122*4882a593Smuzhiyun #gpio-cells = <2>; 123*4882a593Smuzhiyun gpio-controller; 124*4882a593Smuzhiyun #interrupt-cells = <2>; 125*4882a593Smuzhiyun interrupt-controller; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun gpio3: gpio@49010000 { 129*4882a593Smuzhiyun compatible = "ti,omap2-gpio"; 130*4882a593Smuzhiyun reg = <0x49010000 0x200>; 131*4882a593Smuzhiyun interrupts = <31>; 132*4882a593Smuzhiyun ti,hwmods = "gpio3"; 133*4882a593Smuzhiyun ti,gpio-always-on; 134*4882a593Smuzhiyun #gpio-cells = <2>; 135*4882a593Smuzhiyun gpio-controller; 136*4882a593Smuzhiyun #interrupt-cells = <2>; 137*4882a593Smuzhiyun interrupt-controller; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun gpio4: gpio@49012000 { 141*4882a593Smuzhiyun compatible = "ti,omap2-gpio"; 142*4882a593Smuzhiyun reg = <0x49012000 0x200>; 143*4882a593Smuzhiyun interrupts = <32>; 144*4882a593Smuzhiyun ti,hwmods = "gpio4"; 145*4882a593Smuzhiyun ti,gpio-always-on; 146*4882a593Smuzhiyun #gpio-cells = <2>; 147*4882a593Smuzhiyun gpio-controller; 148*4882a593Smuzhiyun #interrupt-cells = <2>; 149*4882a593Smuzhiyun interrupt-controller; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun gpio5: gpio@480b6000 { 153*4882a593Smuzhiyun compatible = "ti,omap2-gpio"; 154*4882a593Smuzhiyun reg = <0x480b6000 0x200>; 155*4882a593Smuzhiyun interrupts = <33>; 156*4882a593Smuzhiyun ti,hwmods = "gpio5"; 157*4882a593Smuzhiyun #gpio-cells = <2>; 158*4882a593Smuzhiyun gpio-controller; 159*4882a593Smuzhiyun #interrupt-cells = <2>; 160*4882a593Smuzhiyun interrupt-controller; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun gpmc: gpmc@6e000000 { 164*4882a593Smuzhiyun compatible = "ti,omap2430-gpmc"; 165*4882a593Smuzhiyun reg = <0x6e000000 0x1000>; 166*4882a593Smuzhiyun #address-cells = <2>; 167*4882a593Smuzhiyun #size-cells = <1>; 168*4882a593Smuzhiyun interrupts = <20>; 169*4882a593Smuzhiyun gpmc,num-cs = <8>; 170*4882a593Smuzhiyun gpmc,num-waitpins = <4>; 171*4882a593Smuzhiyun ti,hwmods = "gpmc"; 172*4882a593Smuzhiyun interrupt-controller; 173*4882a593Smuzhiyun #interrupt-cells = <2>; 174*4882a593Smuzhiyun gpio-controller; 175*4882a593Smuzhiyun #gpio-cells = <2>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun mcbsp1: mcbsp@48074000 { 179*4882a593Smuzhiyun compatible = "ti,omap2430-mcbsp"; 180*4882a593Smuzhiyun reg = <0x48074000 0xff>; 181*4882a593Smuzhiyun reg-names = "mpu"; 182*4882a593Smuzhiyun interrupts = <64>, /* OCP compliant interrupt */ 183*4882a593Smuzhiyun <59>, /* TX interrupt */ 184*4882a593Smuzhiyun <60>, /* RX interrupt */ 185*4882a593Smuzhiyun <61>; /* RX overflow interrupt */ 186*4882a593Smuzhiyun interrupt-names = "common", "tx", "rx", "rx_overflow"; 187*4882a593Smuzhiyun ti,buffer-size = <128>; 188*4882a593Smuzhiyun ti,hwmods = "mcbsp1"; 189*4882a593Smuzhiyun dmas = <&sdma 31>, 190*4882a593Smuzhiyun <&sdma 32>; 191*4882a593Smuzhiyun dma-names = "tx", "rx"; 192*4882a593Smuzhiyun status = "disabled"; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun mcbsp2: mcbsp@48076000 { 196*4882a593Smuzhiyun compatible = "ti,omap2430-mcbsp"; 197*4882a593Smuzhiyun reg = <0x48076000 0xff>; 198*4882a593Smuzhiyun reg-names = "mpu"; 199*4882a593Smuzhiyun interrupts = <16>, /* OCP compliant interrupt */ 200*4882a593Smuzhiyun <62>, /* TX interrupt */ 201*4882a593Smuzhiyun <63>; /* RX interrupt */ 202*4882a593Smuzhiyun interrupt-names = "common", "tx", "rx"; 203*4882a593Smuzhiyun ti,buffer-size = <128>; 204*4882a593Smuzhiyun ti,hwmods = "mcbsp2"; 205*4882a593Smuzhiyun dmas = <&sdma 33>, 206*4882a593Smuzhiyun <&sdma 34>; 207*4882a593Smuzhiyun dma-names = "tx", "rx"; 208*4882a593Smuzhiyun status = "disabled"; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun mcbsp3: mcbsp@4808c000 { 212*4882a593Smuzhiyun compatible = "ti,omap2430-mcbsp"; 213*4882a593Smuzhiyun reg = <0x4808c000 0xff>; 214*4882a593Smuzhiyun reg-names = "mpu"; 215*4882a593Smuzhiyun interrupts = <17>, /* OCP compliant interrupt */ 216*4882a593Smuzhiyun <89>, /* TX interrupt */ 217*4882a593Smuzhiyun <90>; /* RX interrupt */ 218*4882a593Smuzhiyun interrupt-names = "common", "tx", "rx"; 219*4882a593Smuzhiyun ti,buffer-size = <128>; 220*4882a593Smuzhiyun ti,hwmods = "mcbsp3"; 221*4882a593Smuzhiyun dmas = <&sdma 17>, 222*4882a593Smuzhiyun <&sdma 18>; 223*4882a593Smuzhiyun dma-names = "tx", "rx"; 224*4882a593Smuzhiyun status = "disabled"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun mcbsp4: mcbsp@4808e000 { 228*4882a593Smuzhiyun compatible = "ti,omap2430-mcbsp"; 229*4882a593Smuzhiyun reg = <0x4808e000 0xff>; 230*4882a593Smuzhiyun reg-names = "mpu"; 231*4882a593Smuzhiyun interrupts = <18>, /* OCP compliant interrupt */ 232*4882a593Smuzhiyun <54>, /* TX interrupt */ 233*4882a593Smuzhiyun <55>; /* RX interrupt */ 234*4882a593Smuzhiyun interrupt-names = "common", "tx", "rx"; 235*4882a593Smuzhiyun ti,buffer-size = <128>; 236*4882a593Smuzhiyun ti,hwmods = "mcbsp4"; 237*4882a593Smuzhiyun dmas = <&sdma 19>, 238*4882a593Smuzhiyun <&sdma 20>; 239*4882a593Smuzhiyun dma-names = "tx", "rx"; 240*4882a593Smuzhiyun status = "disabled"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun mcbsp5: mcbsp@48096000 { 244*4882a593Smuzhiyun compatible = "ti,omap2430-mcbsp"; 245*4882a593Smuzhiyun reg = <0x48096000 0xff>; 246*4882a593Smuzhiyun reg-names = "mpu"; 247*4882a593Smuzhiyun interrupts = <19>, /* OCP compliant interrupt */ 248*4882a593Smuzhiyun <81>, /* TX interrupt */ 249*4882a593Smuzhiyun <82>; /* RX interrupt */ 250*4882a593Smuzhiyun interrupt-names = "common", "tx", "rx"; 251*4882a593Smuzhiyun ti,buffer-size = <128>; 252*4882a593Smuzhiyun ti,hwmods = "mcbsp5"; 253*4882a593Smuzhiyun dmas = <&sdma 21>, 254*4882a593Smuzhiyun <&sdma 22>; 255*4882a593Smuzhiyun dma-names = "tx", "rx"; 256*4882a593Smuzhiyun status = "disabled"; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun mmc1: mmc@4809c000 { 260*4882a593Smuzhiyun compatible = "ti,omap2-hsmmc"; 261*4882a593Smuzhiyun reg = <0x4809c000 0x200>; 262*4882a593Smuzhiyun interrupts = <83>; 263*4882a593Smuzhiyun ti,hwmods = "mmc1"; 264*4882a593Smuzhiyun ti,dual-volt; 265*4882a593Smuzhiyun dmas = <&sdma 61>, <&sdma 62>; 266*4882a593Smuzhiyun dma-names = "tx", "rx"; 267*4882a593Smuzhiyun pbias-supply = <&pbias_mmc_reg>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun mmc2: mmc@480b4000 { 271*4882a593Smuzhiyun compatible = "ti,omap2-hsmmc"; 272*4882a593Smuzhiyun reg = <0x480b4000 0x200>; 273*4882a593Smuzhiyun interrupts = <86>; 274*4882a593Smuzhiyun ti,hwmods = "mmc2"; 275*4882a593Smuzhiyun dmas = <&sdma 47>, <&sdma 48>; 276*4882a593Smuzhiyun dma-names = "tx", "rx"; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun mailbox: mailbox@48094000 { 280*4882a593Smuzhiyun compatible = "ti,omap2-mailbox"; 281*4882a593Smuzhiyun reg = <0x48094000 0x200>; 282*4882a593Smuzhiyun interrupts = <26>; 283*4882a593Smuzhiyun ti,hwmods = "mailbox"; 284*4882a593Smuzhiyun #mbox-cells = <1>; 285*4882a593Smuzhiyun ti,mbox-num-users = <4>; 286*4882a593Smuzhiyun ti,mbox-num-fifos = <6>; 287*4882a593Smuzhiyun mbox_dsp: dsp { 288*4882a593Smuzhiyun ti,mbox-tx = <0 0 0>; 289*4882a593Smuzhiyun ti,mbox-rx = <1 0 0>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun timer1_target: target-module@49018000 { 294*4882a593Smuzhiyun compatible = "ti,sysc-omap2-timer", "ti,sysc"; 295*4882a593Smuzhiyun reg = <0x49018000 0x4>, 296*4882a593Smuzhiyun <0x49018010 0x4>, 297*4882a593Smuzhiyun <0x49018014 0x4>; 298*4882a593Smuzhiyun reg-names = "rev", "sysc", "syss"; 299*4882a593Smuzhiyun ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 300*4882a593Smuzhiyun SYSC_OMAP2_EMUFREE | 301*4882a593Smuzhiyun SYSC_OMAP2_ENAWAKEUP | 302*4882a593Smuzhiyun SYSC_OMAP2_SOFTRESET | 303*4882a593Smuzhiyun SYSC_OMAP2_AUTOIDLE)>; 304*4882a593Smuzhiyun ti,sysc-sidle = <SYSC_IDLE_FORCE>, 305*4882a593Smuzhiyun <SYSC_IDLE_NO>, 306*4882a593Smuzhiyun <SYSC_IDLE_SMART>; 307*4882a593Smuzhiyun ti,syss-mask = <1>; 308*4882a593Smuzhiyun clocks = <&gpt1_fck>, <&gpt1_ick>; 309*4882a593Smuzhiyun clock-names = "fck", "ick"; 310*4882a593Smuzhiyun #address-cells = <1>; 311*4882a593Smuzhiyun #size-cells = <1>; 312*4882a593Smuzhiyun ranges = <0x0 0x49018000 0x1000>; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun timer1: timer@0 { 315*4882a593Smuzhiyun compatible = "ti,omap2420-timer"; 316*4882a593Smuzhiyun reg = <0 0x400>; 317*4882a593Smuzhiyun interrupts = <37>; 318*4882a593Smuzhiyun ti,timer-alwon; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun mcspi3: spi@480b8000 { 323*4882a593Smuzhiyun compatible = "ti,omap2-mcspi"; 324*4882a593Smuzhiyun ti,hwmods = "mcspi3"; 325*4882a593Smuzhiyun reg = <0x480b8000 0x100>; 326*4882a593Smuzhiyun interrupts = <91>; 327*4882a593Smuzhiyun dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; 328*4882a593Smuzhiyun dma-names = "tx0", "rx0", "tx1", "rx1"; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun usb_otg_hs: usb_otg_hs@480ac000 { 332*4882a593Smuzhiyun compatible = "ti,omap2-musb"; 333*4882a593Smuzhiyun ti,hwmods = "usb_otg_hs"; 334*4882a593Smuzhiyun reg = <0x480ac000 0x1000>; 335*4882a593Smuzhiyun interrupts = <93>; 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun wd_timer2: wdt@49016000 { 339*4882a593Smuzhiyun compatible = "ti,omap2-wdt"; 340*4882a593Smuzhiyun ti,hwmods = "wd_timer2"; 341*4882a593Smuzhiyun reg = <0x49016000 0x80>; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&sdma { 347*4882a593Smuzhiyun compatible = "ti,omap2430-sdma", "ti,omap-sdma"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&i2c1 { 351*4882a593Smuzhiyun compatible = "ti,omap2430-i2c"; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&i2c2 { 355*4882a593Smuzhiyun compatible = "ti,omap2430-i2c"; 356*4882a593Smuzhiyun}; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun#include "omap24xx-clocks.dtsi" 359*4882a593Smuzhiyun#include "omap2430-clocks.dtsi" 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun/* Preferred always-on timer for clockevent */ 362*4882a593Smuzhiyun&timer1_target { 363*4882a593Smuzhiyun ti,no-reset-on-init; 364*4882a593Smuzhiyun ti,no-idle; 365*4882a593Smuzhiyun timer@0 { 366*4882a593Smuzhiyun assigned-clocks = <&gpt1_fck>; 367*4882a593Smuzhiyun assigned-clock-parents = <&func_32k_ck>; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun}; 370