1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com 3*4882a593Smuzhiyun// Copyright 2018 Google, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include "nuvoton-common-npcm7xx.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <1>; 10*4882a593Smuzhiyun interrupt-parent = <&gic>; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun cpus { 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <0>; 15*4882a593Smuzhiyun enable-method = "nuvoton,npcm750-smp"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu@0 { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 20*4882a593Smuzhiyun clocks = <&clk 0>; 21*4882a593Smuzhiyun clock-names = "clk_cpu"; 22*4882a593Smuzhiyun reg = <0>; 23*4882a593Smuzhiyun next-level-cache = <&l2>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun cpu@1 { 27*4882a593Smuzhiyun device_type = "cpu"; 28*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 29*4882a593Smuzhiyun clocks = <&clk 0>; 30*4882a593Smuzhiyun clock-names = "clk_cpu"; 31*4882a593Smuzhiyun reg = <1>; 32*4882a593Smuzhiyun next-level-cache = <&l2>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun soc { 36*4882a593Smuzhiyun timer@3fe600 { 37*4882a593Smuzhiyun compatible = "arm,cortex-a9-twd-timer"; 38*4882a593Smuzhiyun reg = <0x3fe600 0x20>; 39*4882a593Smuzhiyun interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 40*4882a593Smuzhiyun IRQ_TYPE_LEVEL_HIGH)>; 41*4882a593Smuzhiyun clocks = <&clk 5>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun}; 45