xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/nspire.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun *  linux/arch/arm/boot/nspire.dtsi
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	#address-cells = <1>;
10*4882a593Smuzhiyun	#size-cells = <1>;
11*4882a593Smuzhiyun	interrupt-parent = <&intc>;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	cpus {
14*4882a593Smuzhiyun		cpu@0 {
15*4882a593Smuzhiyun			compatible = "arm,arm926ej-s";
16*4882a593Smuzhiyun		};
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	bootrom: bootrom@0 {
20*4882a593Smuzhiyun		reg = <0x00000000 0x80000>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	sram: sram@A4000000 {
24*4882a593Smuzhiyun		device = "memory";
25*4882a593Smuzhiyun		reg = <0xA4000000 0x20000>;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	timer_clk: timer_clk {
29*4882a593Smuzhiyun		#clock-cells = <0>;
30*4882a593Smuzhiyun		compatible = "fixed-clock";
31*4882a593Smuzhiyun		clock-frequency = <32768>;
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	base_clk: base_clk {
35*4882a593Smuzhiyun		#clock-cells = <0>;
36*4882a593Smuzhiyun		reg = <0x900B0024 0x4>;
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	ahb_clk: ahb_clk {
40*4882a593Smuzhiyun		#clock-cells = <0>;
41*4882a593Smuzhiyun		reg = <0x900B0024 0x4>;
42*4882a593Smuzhiyun		clocks = <&base_clk>;
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	apb_pclk: apb_pclk {
46*4882a593Smuzhiyun		#clock-cells = <0>;
47*4882a593Smuzhiyun		compatible = "fixed-factor-clock";
48*4882a593Smuzhiyun		clock-div = <2>;
49*4882a593Smuzhiyun		clock-mult = <1>;
50*4882a593Smuzhiyun		clocks = <&ahb_clk>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	usb_phy: usb_phy {
54*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
55*4882a593Smuzhiyun		#phy-cells = <0>;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	vbus_reg: vbus_reg {
59*4882a593Smuzhiyun		compatible = "regulator-fixed";
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		regulator-name = "USB VBUS output";
62*4882a593Smuzhiyun		regulator-type = "voltage";
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
65*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	ahb {
69*4882a593Smuzhiyun		compatible = "simple-bus";
70*4882a593Smuzhiyun		#address-cells = <1>;
71*4882a593Smuzhiyun		#size-cells = <1>;
72*4882a593Smuzhiyun		ranges;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		spi: spi@A9000000 {
75*4882a593Smuzhiyun			reg = <0xA9000000 0x1000>;
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		usb0: usb@B0000000 {
79*4882a593Smuzhiyun			compatible = "lsi,zevio-usb";
80*4882a593Smuzhiyun			reg = <0xB0000000 0x1000>;
81*4882a593Smuzhiyun			interrupts = <8>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun			usb-phy = <&usb_phy>;
84*4882a593Smuzhiyun			vbus-supply = <&vbus_reg>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		usb1: usb@B4000000 {
88*4882a593Smuzhiyun			reg = <0xB4000000 0x1000>;
89*4882a593Smuzhiyun			interrupts = <9>;
90*4882a593Smuzhiyun			status = "disabled";
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		lcd: lcd@C0000000 {
94*4882a593Smuzhiyun			compatible = "arm,pl111", "arm,primecell";
95*4882a593Smuzhiyun			reg = <0xC0000000 0x1000>;
96*4882a593Smuzhiyun			interrupts = <21>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			/*
99*4882a593Smuzhiyun			 * We assume the same clock is fed to APB and CLCDCLK.
100*4882a593Smuzhiyun			 * There is some code to scale the clock down by a factor
101*4882a593Smuzhiyun			 * 48 for the display so likely the frequency to the
102*4882a593Smuzhiyun			 * display is 1MHz and the CLCDCLK is 48 MHz.
103*4882a593Smuzhiyun			 */
104*4882a593Smuzhiyun			clocks = <&apb_pclk>, <&apb_pclk>;
105*4882a593Smuzhiyun			clock-names = "clcdclk", "apb_pclk";
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		adc: adc@C4000000 {
109*4882a593Smuzhiyun			reg = <0xC4000000 0x1000>;
110*4882a593Smuzhiyun			interrupts = <11>;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun		tdes: crypto@C8010000 {
114*4882a593Smuzhiyun			reg = <0xC8010000 0x1000>;
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		sha256: crypto@CC000000 {
118*4882a593Smuzhiyun			reg = <0xCC000000 0x1000>;
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		apb@90000000 {
122*4882a593Smuzhiyun			compatible = "simple-bus";
123*4882a593Smuzhiyun			#address-cells = <1>;
124*4882a593Smuzhiyun			#size-cells = <1>;
125*4882a593Smuzhiyun			clock-ranges;
126*4882a593Smuzhiyun			ranges;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun			gpio: gpio@90000000 {
129*4882a593Smuzhiyun				compatible = "lsi,zevio-gpio";
130*4882a593Smuzhiyun				reg = <0x90000000 0x1000>;
131*4882a593Smuzhiyun				interrupts = <7>;
132*4882a593Smuzhiyun				gpio-controller;
133*4882a593Smuzhiyun				#gpio-cells = <2>;
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun			fast_timer: timer@90010000 {
137*4882a593Smuzhiyun				reg = <0x90010000 0x1000>;
138*4882a593Smuzhiyun				interrupts = <17>;
139*4882a593Smuzhiyun			};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun			uart: serial@90020000 {
142*4882a593Smuzhiyun				reg = <0x90020000 0x1000>;
143*4882a593Smuzhiyun				interrupts = <1>;
144*4882a593Smuzhiyun			};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun			timer0: timer@900C0000 {
147*4882a593Smuzhiyun				reg = <0x900C0000 0x1000>;
148*4882a593Smuzhiyun				clocks = <&timer_clk>, <&timer_clk>,
149*4882a593Smuzhiyun					 <&timer_clk>;
150*4882a593Smuzhiyun				clock-names = "timer0clk", "timer1clk",
151*4882a593Smuzhiyun					      "apb_pclk";
152*4882a593Smuzhiyun			};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun			timer1: timer@900D0000 {
155*4882a593Smuzhiyun				reg = <0x900D0000 0x1000>;
156*4882a593Smuzhiyun				interrupts = <19>;
157*4882a593Smuzhiyun				clocks = <&timer_clk>, <&timer_clk>,
158*4882a593Smuzhiyun					 <&timer_clk>;
159*4882a593Smuzhiyun				clock-names = "timer0clk", "timer1clk",
160*4882a593Smuzhiyun					      "apb_pclk";
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			watchdog: watchdog@90060000 {
164*4882a593Smuzhiyun				compatible = "arm,amba-primecell";
165*4882a593Smuzhiyun				reg = <0x90060000 0x1000>;
166*4882a593Smuzhiyun				interrupts = <3>;
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			rtc: rtc@90090000 {
170*4882a593Smuzhiyun				reg = <0x90090000 0x1000>;
171*4882a593Smuzhiyun				interrupts = <4>;
172*4882a593Smuzhiyun			};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun			misc: misc@900A0000 {
175*4882a593Smuzhiyun				reg = <0x900A0000 0x1000>;
176*4882a593Smuzhiyun			};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun			pwr: pwr@900B0000 {
179*4882a593Smuzhiyun				reg = <0x900B0000 0x1000>;
180*4882a593Smuzhiyun				interrupts = <15>;
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun			keypad: input@900E0000 {
184*4882a593Smuzhiyun				compatible = "ti,nspire-keypad";
185*4882a593Smuzhiyun				reg = <0x900E0000 0x1000>;
186*4882a593Smuzhiyun				interrupts = <16>;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun				scan-interval = <1000>;
189*4882a593Smuzhiyun				row-delay = <200>;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun				clocks = <&apb_pclk>;
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun			contrast: contrast@900F0000 {
195*4882a593Smuzhiyun				reg = <0x900F0000 0x1000>;
196*4882a593Smuzhiyun			};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun			led: led@90110000 {
199*4882a593Smuzhiyun				reg = <0x90110000 0x1000>;
200*4882a593Smuzhiyun			};
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun};
204