xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/nspire-cx.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun *  linux/arch/arm/boot/nspire-cx.dts
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/include/ "nspire.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun&lcd {
12*4882a593Smuzhiyun	port {
13*4882a593Smuzhiyun		clcd_pads: endpoint {
14*4882a593Smuzhiyun			remote-endpoint = <&panel_in>;
15*4882a593Smuzhiyun		};
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun&fast_timer {
20*4882a593Smuzhiyun	/* compatible = "arm,sp804", "arm,primecell"; */
21*4882a593Smuzhiyun};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun&uart {
24*4882a593Smuzhiyun	compatible = "arm,pl011", "arm,primecell";
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	clocks = <&uart_clk>, <&apb_pclk>;
27*4882a593Smuzhiyun	clock-names = "uart_clk", "apb_pclk";
28*4882a593Smuzhiyun};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun&timer0 {
31*4882a593Smuzhiyun	compatible = "arm,sp804", "arm,primecell";
32*4882a593Smuzhiyun};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun&timer1 {
35*4882a593Smuzhiyun	compatible = "arm,sp804", "arm,primecell";
36*4882a593Smuzhiyun};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun&base_clk {
39*4882a593Smuzhiyun	compatible = "lsi,nspire-cx-clock";
40*4882a593Smuzhiyun};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun&ahb_clk {
43*4882a593Smuzhiyun	compatible = "lsi,nspire-cx-ahb-divider";
44*4882a593Smuzhiyun};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun&keypad {
47*4882a593Smuzhiyun	linux,keymap = <
48*4882a593Smuzhiyun	0x0000001c 	0x0001001c 	0x00040039
49*4882a593Smuzhiyun	0x0005002c 	0x00060015 	0x0007000b
50*4882a593Smuzhiyun	0x0008000f 	0x0100002d 	0x01010011
51*4882a593Smuzhiyun	0x0102002f 	0x01030004 	0x01040016
52*4882a593Smuzhiyun	0x01050014 	0x0106001f 	0x01070002
53*4882a593Smuzhiyun	0x010a006a 	0x02000013 	0x02010010
54*4882a593Smuzhiyun	0x02020019 	0x02030007 	0x02040018
55*4882a593Smuzhiyun	0x02050031 	0x02060032 	0x02070005
56*4882a593Smuzhiyun	0x02080028 	0x0209006c 	0x03000026
57*4882a593Smuzhiyun	0x03010025 	0x03020024 	0x0303000a
58*4882a593Smuzhiyun	0x03040017 	0x03050023 	0x03060022
59*4882a593Smuzhiyun	0x03070008 	0x03080035 	0x03090069
60*4882a593Smuzhiyun	0x04000021 	0x04010012 	0x04020020
61*4882a593Smuzhiyun	0x0404002e 	0x04050030 	0x0406001e
62*4882a593Smuzhiyun	0x0407000d 	0x04080037 	0x04090067
63*4882a593Smuzhiyun	0x05010038 	0x0502000c 	0x0503001b
64*4882a593Smuzhiyun	0x05040034 	0x0505001a 	0x05060006
65*4882a593Smuzhiyun	0x05080027 	0x0509000e 	0x050a006f
66*4882a593Smuzhiyun	0x0600002b 	0x0602004e 	0x06030068
67*4882a593Smuzhiyun	0x06040003 	0x0605006d 	0x06060009
68*4882a593Smuzhiyun	0x06070001 	0x0609000f 	0x0708002a
69*4882a593Smuzhiyun	0x0709001d 	0x070a0033 	>;
70*4882a593Smuzhiyun};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun&vbus_reg {
73*4882a593Smuzhiyun	gpio = <&gpio 2 0>;
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun/ {
77*4882a593Smuzhiyun	model = "TI-NSPIRE CX";
78*4882a593Smuzhiyun	compatible = "ti,nspire-cx";
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	memory {
81*4882a593Smuzhiyun		device_type = "memory";
82*4882a593Smuzhiyun		reg = <0x10000000 0x4000000>; /* 64 MB */
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	uart_clk: uart_clk {
86*4882a593Smuzhiyun		#clock-cells = <0>;
87*4882a593Smuzhiyun		compatible = "fixed-clock";
88*4882a593Smuzhiyun		clock-frequency = <12000000>;
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	ahb {
92*4882a593Smuzhiyun		#address-cells = <1>;
93*4882a593Smuzhiyun		#size-cells = <1>;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		intc: interrupt-controller@DC000000 {
96*4882a593Smuzhiyun			compatible = "arm,pl190-vic";
97*4882a593Smuzhiyun			interrupt-controller;
98*4882a593Smuzhiyun			reg = <0xDC000000 0x1000>;
99*4882a593Smuzhiyun			#interrupt-cells = <1>;
100*4882a593Smuzhiyun		};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		apb@90000000 {
103*4882a593Smuzhiyun			#address-cells = <1>;
104*4882a593Smuzhiyun			#size-cells = <1>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun			i2c@90050000 {
107*4882a593Smuzhiyun				compatible = "snps,designware-i2c";
108*4882a593Smuzhiyun				reg = <0x90050000 0x1000>;
109*4882a593Smuzhiyun				interrupts = <20>;
110*4882a593Smuzhiyun			};
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	panel {
115*4882a593Smuzhiyun		compatible = "ti,nspire-cx-lcd-panel";
116*4882a593Smuzhiyun		port {
117*4882a593Smuzhiyun			panel_in: endpoint {
118*4882a593Smuzhiyun				remote-endpoint = <&clcd_pads>;
119*4882a593Smuzhiyun			};
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun	chosen {
123*4882a593Smuzhiyun		bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun};
126