1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017-2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Sean Wang <sean.wang@mediatek.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "mt7623n.dtsi" 11*4882a593Smuzhiyun#include "mt6323.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "MediaTek MT7623N with eMMC reference board"; 15*4882a593Smuzhiyun compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun aliases { 18*4882a593Smuzhiyun serial0 = &uart0; 19*4882a593Smuzhiyun serial1 = &uart1; 20*4882a593Smuzhiyun serial2 = &uart2; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun chosen { 24*4882a593Smuzhiyun stdout-path = "serial2:115200n8"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun connector { 28*4882a593Smuzhiyun compatible = "hdmi-connector"; 29*4882a593Smuzhiyun label = "hdmi"; 30*4882a593Smuzhiyun type = "d"; 31*4882a593Smuzhiyun ddc-i2c-bus = <&hdmiddc0>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun port { 34*4882a593Smuzhiyun hdmi_connector_in: endpoint { 35*4882a593Smuzhiyun remote-endpoint = <&hdmi0_out>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cpus { 41*4882a593Smuzhiyun cpu@0 { 42*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun cpu@1 { 46*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun cpu@2 { 50*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun cpu@3 { 54*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun gpio-keys { 59*4882a593Smuzhiyun compatible = "gpio-keys"; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun pinctrl-0 = <&key_pins_a>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun factory { 64*4882a593Smuzhiyun label = "factory"; 65*4882a593Smuzhiyun linux,code = <BTN_0>; 66*4882a593Smuzhiyun gpios = <&pio 256 GPIO_ACTIVE_LOW>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun wps { 70*4882a593Smuzhiyun label = "wps"; 71*4882a593Smuzhiyun linux,code = <KEY_WPS_BUTTON>; 72*4882a593Smuzhiyun gpios = <&pio 257 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun memory@80000000 { 77*4882a593Smuzhiyun device_type = "memory"; 78*4882a593Smuzhiyun reg = <0 0x80000000 0 0x40000000>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun reg_1p8v: regulator-1p8v { 82*4882a593Smuzhiyun compatible = "regulator-fixed"; 83*4882a593Smuzhiyun regulator-name = "fixed-1.8V"; 84*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 85*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 86*4882a593Smuzhiyun regulator-boot-on; 87*4882a593Smuzhiyun regulator-always-on; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 91*4882a593Smuzhiyun compatible = "regulator-fixed"; 92*4882a593Smuzhiyun regulator-name = "fixed-3.3V"; 93*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 94*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 95*4882a593Smuzhiyun regulator-boot-on; 96*4882a593Smuzhiyun regulator-always-on; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun reg_5v: regulator-5v { 100*4882a593Smuzhiyun compatible = "regulator-fixed"; 101*4882a593Smuzhiyun regulator-name = "fixed-5V"; 102*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 103*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 104*4882a593Smuzhiyun regulator-boot-on; 105*4882a593Smuzhiyun regulator-always-on; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun sound { 109*4882a593Smuzhiyun compatible = "mediatek,mt2701-wm8960-machine"; 110*4882a593Smuzhiyun mediatek,platform = <&afe>; 111*4882a593Smuzhiyun audio-routing = 112*4882a593Smuzhiyun "Headphone", "HP_L", 113*4882a593Smuzhiyun "Headphone", "HP_R", 114*4882a593Smuzhiyun "LINPUT1", "AMIC", 115*4882a593Smuzhiyun "RINPUT1", "AMIC"; 116*4882a593Smuzhiyun mediatek,audio-codec = <&wm8960>; 117*4882a593Smuzhiyun pinctrl-names = "default"; 118*4882a593Smuzhiyun pinctrl-0 = <&i2s0_pins_a>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&bls { 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&btif { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&cec { 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&cir { 135*4882a593Smuzhiyun pinctrl-names = "default"; 136*4882a593Smuzhiyun pinctrl-0 = <&cir_pins_a>; 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&crypto { 141*4882a593Smuzhiyun status = "okay"; 142*4882a593Smuzhiyun}; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&dpi0 { 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun ports { 148*4882a593Smuzhiyun #address-cells = <1>; 149*4882a593Smuzhiyun #size-cells = <0>; 150*4882a593Smuzhiyun port@0 { 151*4882a593Smuzhiyun reg = <0>; 152*4882a593Smuzhiyun dpi0_out: endpoint { 153*4882a593Smuzhiyun remote-endpoint = <&hdmi0_in>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyunð { 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun gmac0: mac@0 { 163*4882a593Smuzhiyun compatible = "mediatek,eth-mac"; 164*4882a593Smuzhiyun reg = <0>; 165*4882a593Smuzhiyun phy-mode = "trgmii"; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun fixed-link { 168*4882a593Smuzhiyun speed = <1000>; 169*4882a593Smuzhiyun full-duplex; 170*4882a593Smuzhiyun pause; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun mac@1 { 175*4882a593Smuzhiyun compatible = "mediatek,eth-mac"; 176*4882a593Smuzhiyun reg = <1>; 177*4882a593Smuzhiyun phy-mode = "rgmii"; 178*4882a593Smuzhiyun phy-handle = <&phy5>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun mdio-bus { 182*4882a593Smuzhiyun #address-cells = <1>; 183*4882a593Smuzhiyun #size-cells = <0>; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun phy5: ethernet-phy@5 { 186*4882a593Smuzhiyun reg = <5>; 187*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun switch@0 { 191*4882a593Smuzhiyun compatible = "mediatek,mt7530"; 192*4882a593Smuzhiyun reg = <0>; 193*4882a593Smuzhiyun reset-gpios = <&pio 33 0>; 194*4882a593Smuzhiyun core-supply = <&mt6323_vpa_reg>; 195*4882a593Smuzhiyun io-supply = <&mt6323_vemc3v3_reg>; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun ports { 198*4882a593Smuzhiyun #address-cells = <1>; 199*4882a593Smuzhiyun #size-cells = <0>; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun port@0 { 202*4882a593Smuzhiyun reg = <0>; 203*4882a593Smuzhiyun label = "lan0"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun port@1 { 207*4882a593Smuzhiyun reg = <1>; 208*4882a593Smuzhiyun label = "lan1"; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun port@2 { 212*4882a593Smuzhiyun reg = <2>; 213*4882a593Smuzhiyun label = "lan2"; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun port@3 { 217*4882a593Smuzhiyun reg = <3>; 218*4882a593Smuzhiyun label = "lan3"; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun port@4 { 222*4882a593Smuzhiyun reg = <4>; 223*4882a593Smuzhiyun label = "wan"; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun port@6 { 227*4882a593Smuzhiyun reg = <6>; 228*4882a593Smuzhiyun label = "cpu"; 229*4882a593Smuzhiyun ethernet = <&gmac0>; 230*4882a593Smuzhiyun phy-mode = "trgmii"; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun fixed-link { 233*4882a593Smuzhiyun speed = <1000>; 234*4882a593Smuzhiyun full-duplex; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&hdmi0 { 243*4882a593Smuzhiyun pinctrl-names = "default"; 244*4882a593Smuzhiyun pinctrl-0 = <&hdmi_pins_a>; 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun ports { 248*4882a593Smuzhiyun #address-cells = <1>; 249*4882a593Smuzhiyun #size-cells = <0>; 250*4882a593Smuzhiyun port@0 { 251*4882a593Smuzhiyun reg = <0>; 252*4882a593Smuzhiyun hdmi0_in: endpoint { 253*4882a593Smuzhiyun remote-endpoint = <&dpi0_out>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun port@1 { 258*4882a593Smuzhiyun reg = <1>; 259*4882a593Smuzhiyun hdmi0_out: endpoint { 260*4882a593Smuzhiyun remote-endpoint = <&hdmi_connector_in>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&hdmiddc0 { 267*4882a593Smuzhiyun pinctrl-names = "default"; 268*4882a593Smuzhiyun pinctrl-0 = <&hdmi_ddc_pins_a>; 269*4882a593Smuzhiyun status = "okay"; 270*4882a593Smuzhiyun}; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun&hdmi_phy { 273*4882a593Smuzhiyun mediatek,ibias = <0xa>; 274*4882a593Smuzhiyun mediatek,ibias_up = <0x1c>; 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&i2c0 { 279*4882a593Smuzhiyun pinctrl-names = "default"; 280*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins_a>; 281*4882a593Smuzhiyun status = "okay"; 282*4882a593Smuzhiyun}; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun&i2c1 { 285*4882a593Smuzhiyun pinctrl-names = "default"; 286*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins_b>; 287*4882a593Smuzhiyun status = "okay"; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun wm8960: wm8960@1a { 290*4882a593Smuzhiyun compatible = "wlf,wm8960"; 291*4882a593Smuzhiyun reg = <0x1a>; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun&i2c2 { 296*4882a593Smuzhiyun pinctrl-names = "default"; 297*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins_a>; 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&mmc0 { 302*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 303*4882a593Smuzhiyun pinctrl-0 = <&mmc0_pins_default>; 304*4882a593Smuzhiyun pinctrl-1 = <&mmc0_pins_uhs>; 305*4882a593Smuzhiyun status = "okay"; 306*4882a593Smuzhiyun bus-width = <8>; 307*4882a593Smuzhiyun max-frequency = <50000000>; 308*4882a593Smuzhiyun cap-mmc-highspeed; 309*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 310*4882a593Smuzhiyun vqmmc-supply = <®_1p8v>; 311*4882a593Smuzhiyun non-removable; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&mmc1 { 315*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 316*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins_default>; 317*4882a593Smuzhiyun pinctrl-1 = <&mmc1_pins_uhs>; 318*4882a593Smuzhiyun status = "okay"; 319*4882a593Smuzhiyun bus-width = <4>; 320*4882a593Smuzhiyun max-frequency = <50000000>; 321*4882a593Smuzhiyun cap-sd-highspeed; 322*4882a593Smuzhiyun cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; 323*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 324*4882a593Smuzhiyun vqmmc-supply = <®_3p3v>; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&pcie { 328*4882a593Smuzhiyun pinctrl-names = "default"; 329*4882a593Smuzhiyun pinctrl-0 = <&pcie_default>; 330*4882a593Smuzhiyun status = "okay"; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun pcie@0,0 { 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun pcie@1,0 { 337*4882a593Smuzhiyun status = "okay"; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun}; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun&pcie0_phy { 342*4882a593Smuzhiyun status = "okay"; 343*4882a593Smuzhiyun}; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun&pcie1_phy { 346*4882a593Smuzhiyun status = "okay"; 347*4882a593Smuzhiyun}; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun&pwm { 350*4882a593Smuzhiyun pinctrl-names = "default"; 351*4882a593Smuzhiyun pinctrl-0 = <&pwm_pins_a>; 352*4882a593Smuzhiyun status = "okay"; 353*4882a593Smuzhiyun}; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun&spi0 { 356*4882a593Smuzhiyun pinctrl-names = "default"; 357*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins_a>; 358*4882a593Smuzhiyun status = "okay"; 359*4882a593Smuzhiyun}; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun&spi1 { 362*4882a593Smuzhiyun pinctrl-names = "default"; 363*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins_a>; 364*4882a593Smuzhiyun status = "okay"; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&spi2 { 368*4882a593Smuzhiyun pinctrl-names = "default"; 369*4882a593Smuzhiyun pinctrl-0 = <&spi2_pins_a>; 370*4882a593Smuzhiyun status = "okay"; 371*4882a593Smuzhiyun}; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun&uart0 { 374*4882a593Smuzhiyun pinctrl-names = "default"; 375*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins_a>; 376*4882a593Smuzhiyun status = "okay"; 377*4882a593Smuzhiyun}; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun&uart1 { 380*4882a593Smuzhiyun pinctrl-names = "default"; 381*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins_a>; 382*4882a593Smuzhiyun status = "okay"; 383*4882a593Smuzhiyun}; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun&uart2 { 386*4882a593Smuzhiyun pinctrl-names = "default"; 387*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins_a>; 388*4882a593Smuzhiyun status = "okay"; 389*4882a593Smuzhiyun}; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun&usb1 { 392*4882a593Smuzhiyun vusb33-supply = <®_3p3v>; 393*4882a593Smuzhiyun vbus-supply = <®_5v>; 394*4882a593Smuzhiyun status = "okay"; 395*4882a593Smuzhiyun}; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun&u3phy1 { 398*4882a593Smuzhiyun status = "okay"; 399*4882a593Smuzhiyun}; 400