xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright 2017-2018 Sean Wang <sean.wang@mediatek.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun#include "mt7623n.dtsi"
10*4882a593Smuzhiyun#include "mt6323.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Bananapi BPI-R2";
14*4882a593Smuzhiyun	compatible = "bananapi,bpi-r2", "mediatek,mt7623";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		serial2 = &uart2;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	chosen {
21*4882a593Smuzhiyun		stdout-path = "serial2:115200n8";
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	connector {
25*4882a593Smuzhiyun		compatible = "hdmi-connector";
26*4882a593Smuzhiyun		label = "hdmi";
27*4882a593Smuzhiyun		type = "d";
28*4882a593Smuzhiyun		ddc-i2c-bus = <&hdmiddc0>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		port {
31*4882a593Smuzhiyun			hdmi_connector_in: endpoint {
32*4882a593Smuzhiyun				remote-endpoint = <&hdmi0_out>;
33*4882a593Smuzhiyun			};
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	cpus {
38*4882a593Smuzhiyun		cpu@0 {
39*4882a593Smuzhiyun			proc-supply = <&mt6323_vproc_reg>;
40*4882a593Smuzhiyun		};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun		cpu@1 {
43*4882a593Smuzhiyun			proc-supply = <&mt6323_vproc_reg>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		cpu@2 {
47*4882a593Smuzhiyun			proc-supply = <&mt6323_vproc_reg>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		cpu@3 {
51*4882a593Smuzhiyun			proc-supply = <&mt6323_vproc_reg>;
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	reg_1p8v: regulator-1p8v {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "fixed-1.8V";
58*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
60*4882a593Smuzhiyun		regulator-boot-on;
61*4882a593Smuzhiyun		regulator-always-on;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
65*4882a593Smuzhiyun		compatible = "regulator-fixed";
66*4882a593Smuzhiyun		regulator-name = "fixed-3.3V";
67*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
68*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
69*4882a593Smuzhiyun		regulator-boot-on;
70*4882a593Smuzhiyun		regulator-always-on;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	reg_5v: regulator-5v {
74*4882a593Smuzhiyun		compatible = "regulator-fixed";
75*4882a593Smuzhiyun		regulator-name = "fixed-5V";
76*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
77*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
78*4882a593Smuzhiyun		regulator-boot-on;
79*4882a593Smuzhiyun		regulator-always-on;
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	reg_vgpu: fixedregulator@0 {
83*4882a593Smuzhiyun		compatible = "regulator-fixed";
84*4882a593Smuzhiyun		regulator-name = "vdd_fixed_vgpu";
85*4882a593Smuzhiyun		regulator-min-microvolt = <1150000>;
86*4882a593Smuzhiyun		regulator-max-microvolt = <1150000>;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	gpio-keys {
90*4882a593Smuzhiyun		compatible = "gpio-keys";
91*4882a593Smuzhiyun		pinctrl-names = "default";
92*4882a593Smuzhiyun		pinctrl-0 = <&key_pins_a>;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun		factory {
95*4882a593Smuzhiyun			label = "factory";
96*4882a593Smuzhiyun			linux,code = <BTN_0>;
97*4882a593Smuzhiyun			gpios = <&pio 256 GPIO_ACTIVE_LOW>;
98*4882a593Smuzhiyun		};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		wps {
101*4882a593Smuzhiyun			label = "wps";
102*4882a593Smuzhiyun			linux,code = <KEY_WPS_BUTTON>;
103*4882a593Smuzhiyun			gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	leds {
108*4882a593Smuzhiyun		compatible = "gpio-leds";
109*4882a593Smuzhiyun		pinctrl-names = "default";
110*4882a593Smuzhiyun		pinctrl-0 = <&led_pins_a>;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		blue {
113*4882a593Smuzhiyun			label = "bpi-r2:pio:blue";
114*4882a593Smuzhiyun			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
115*4882a593Smuzhiyun			default-state = "off";
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun		green {
119*4882a593Smuzhiyun			label = "bpi-r2:pio:green";
120*4882a593Smuzhiyun			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
121*4882a593Smuzhiyun			default-state = "off";
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		red {
125*4882a593Smuzhiyun			label = "bpi-r2:pio:red";
126*4882a593Smuzhiyun			gpios = <&pio 239 GPIO_ACTIVE_LOW>;
127*4882a593Smuzhiyun			default-state = "off";
128*4882a593Smuzhiyun		};
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	memory@80000000 {
132*4882a593Smuzhiyun		device_type = "memory";
133*4882a593Smuzhiyun		reg = <0 0x80000000 0 0x80000000>;
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun&bls {
138*4882a593Smuzhiyun	status = "okay";
139*4882a593Smuzhiyun};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun&btif {
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&cec {
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&cir {
150*4882a593Smuzhiyun	pinctrl-names = "default";
151*4882a593Smuzhiyun	pinctrl-0 = <&cir_pins_a>;
152*4882a593Smuzhiyun	status = "okay";
153*4882a593Smuzhiyun};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun&crypto {
156*4882a593Smuzhiyun	status = "okay";
157*4882a593Smuzhiyun};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun&dpi0 {
160*4882a593Smuzhiyun	status = "okay";
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	ports {
163*4882a593Smuzhiyun		#address-cells = <1>;
164*4882a593Smuzhiyun		#size-cells = <0>;
165*4882a593Smuzhiyun		port@0 {
166*4882a593Smuzhiyun			reg = <0>;
167*4882a593Smuzhiyun			dpi0_out: endpoint {
168*4882a593Smuzhiyun				remote-endpoint = <&hdmi0_in>;
169*4882a593Smuzhiyun			};
170*4882a593Smuzhiyun		};
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun&eth {
175*4882a593Smuzhiyun	status = "okay";
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	gmac0: mac@0 {
178*4882a593Smuzhiyun		compatible = "mediatek,eth-mac";
179*4882a593Smuzhiyun		reg = <0>;
180*4882a593Smuzhiyun		phy-mode = "trgmii";
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		fixed-link {
183*4882a593Smuzhiyun			speed = <1000>;
184*4882a593Smuzhiyun			full-duplex;
185*4882a593Smuzhiyun			pause;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	mdio: mdio-bus {
190*4882a593Smuzhiyun		#address-cells = <1>;
191*4882a593Smuzhiyun		#size-cells = <0>;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		switch@0 {
194*4882a593Smuzhiyun			compatible = "mediatek,mt7530";
195*4882a593Smuzhiyun			reg = <0>;
196*4882a593Smuzhiyun			reset-gpios = <&pio 33 0>;
197*4882a593Smuzhiyun			core-supply = <&mt6323_vpa_reg>;
198*4882a593Smuzhiyun			io-supply = <&mt6323_vemc3v3_reg>;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun			ports {
201*4882a593Smuzhiyun				#address-cells = <1>;
202*4882a593Smuzhiyun				#size-cells = <0>;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun				port@0 {
205*4882a593Smuzhiyun					reg = <0>;
206*4882a593Smuzhiyun					label = "wan";
207*4882a593Smuzhiyun				};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun				port@1 {
210*4882a593Smuzhiyun					reg = <1>;
211*4882a593Smuzhiyun					label = "lan0";
212*4882a593Smuzhiyun				};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun				port@2 {
215*4882a593Smuzhiyun					reg = <2>;
216*4882a593Smuzhiyun					label = "lan1";
217*4882a593Smuzhiyun				};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun				port@3 {
220*4882a593Smuzhiyun					reg = <3>;
221*4882a593Smuzhiyun					label = "lan2";
222*4882a593Smuzhiyun				};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun				port@4 {
225*4882a593Smuzhiyun					reg = <4>;
226*4882a593Smuzhiyun					label = "lan3";
227*4882a593Smuzhiyun				};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun				port@6 {
230*4882a593Smuzhiyun					reg = <6>;
231*4882a593Smuzhiyun					label = "cpu";
232*4882a593Smuzhiyun					ethernet = <&gmac0>;
233*4882a593Smuzhiyun					phy-mode = "trgmii";
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun					fixed-link {
236*4882a593Smuzhiyun						speed = <1000>;
237*4882a593Smuzhiyun						full-duplex;
238*4882a593Smuzhiyun						pause;
239*4882a593Smuzhiyun					};
240*4882a593Smuzhiyun				};
241*4882a593Smuzhiyun			};
242*4882a593Smuzhiyun		};
243*4882a593Smuzhiyun	};
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&hdmi0 {
247*4882a593Smuzhiyun	pinctrl-names = "default";
248*4882a593Smuzhiyun	pinctrl-0 = <&hdmi_pins_a>;
249*4882a593Smuzhiyun	status = "okay";
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun	ports {
252*4882a593Smuzhiyun		#address-cells = <1>;
253*4882a593Smuzhiyun		#size-cells = <0>;
254*4882a593Smuzhiyun		port@0 {
255*4882a593Smuzhiyun			reg = <0>;
256*4882a593Smuzhiyun			hdmi0_in: endpoint {
257*4882a593Smuzhiyun				remote-endpoint = <&dpi0_out>;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun		port@1 {
262*4882a593Smuzhiyun			reg = <1>;
263*4882a593Smuzhiyun			hdmi0_out: endpoint {
264*4882a593Smuzhiyun				remote-endpoint = <&hdmi_connector_in>;
265*4882a593Smuzhiyun			};
266*4882a593Smuzhiyun		};
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&hdmiddc0 {
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun	pinctrl-0 = <&hdmi_ddc_pins_a>;
273*4882a593Smuzhiyun	status = "okay";
274*4882a593Smuzhiyun};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun&hdmi_phy {
277*4882a593Smuzhiyun	mediatek,ibias = <0xa>;
278*4882a593Smuzhiyun	mediatek,ibias_up = <0x1c>;
279*4882a593Smuzhiyun	status = "okay";
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&i2c0 {
283*4882a593Smuzhiyun	pinctrl-names = "default";
284*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins_a>;
285*4882a593Smuzhiyun	status = "okay";
286*4882a593Smuzhiyun};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun&i2c1 {
289*4882a593Smuzhiyun	pinctrl-names = "default";
290*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins_a>;
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&mali {
295*4882a593Smuzhiyun	mali-supply = <&reg_vgpu>;
296*4882a593Smuzhiyun	status = "okay";
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&mmc0 {
300*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
301*4882a593Smuzhiyun	pinctrl-0 = <&mmc0_pins_default>;
302*4882a593Smuzhiyun	pinctrl-1 = <&mmc0_pins_uhs>;
303*4882a593Smuzhiyun	status = "okay";
304*4882a593Smuzhiyun	bus-width = <8>;
305*4882a593Smuzhiyun	max-frequency = <50000000>;
306*4882a593Smuzhiyun	cap-mmc-highspeed;
307*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
308*4882a593Smuzhiyun	vqmmc-supply = <&reg_1p8v>;
309*4882a593Smuzhiyun	non-removable;
310*4882a593Smuzhiyun};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun&mmc1 {
313*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
314*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins_default>;
315*4882a593Smuzhiyun	pinctrl-1 = <&mmc1_pins_uhs>;
316*4882a593Smuzhiyun	status = "okay";
317*4882a593Smuzhiyun	bus-width = <4>;
318*4882a593Smuzhiyun	max-frequency = <50000000>;
319*4882a593Smuzhiyun	cap-sd-highspeed;
320*4882a593Smuzhiyun	cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
321*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
322*4882a593Smuzhiyun	vqmmc-supply = <&reg_3p3v>;
323*4882a593Smuzhiyun};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun&mt6323_leds {
326*4882a593Smuzhiyun	status = "okay";
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	led@0 {
329*4882a593Smuzhiyun		reg = <0>;
330*4882a593Smuzhiyun		label = "bpi-r2:isink:green";
331*4882a593Smuzhiyun		default-state = "off";
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	led@1 {
335*4882a593Smuzhiyun		reg = <1>;
336*4882a593Smuzhiyun		label = "bpi-r2:isink:red";
337*4882a593Smuzhiyun		default-state = "off";
338*4882a593Smuzhiyun	};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun	led@2 {
341*4882a593Smuzhiyun		reg = <2>;
342*4882a593Smuzhiyun		label = "bpi-r2:isink:blue";
343*4882a593Smuzhiyun		default-state = "off";
344*4882a593Smuzhiyun	};
345*4882a593Smuzhiyun};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun&pcie {
348*4882a593Smuzhiyun	pinctrl-names = "default";
349*4882a593Smuzhiyun	pinctrl-0 = <&pcie_default>;
350*4882a593Smuzhiyun	status = "okay";
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun	pcie@0,0 {
353*4882a593Smuzhiyun		status = "okay";
354*4882a593Smuzhiyun	};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun	pcie@1,0 {
357*4882a593Smuzhiyun		status = "okay";
358*4882a593Smuzhiyun	};
359*4882a593Smuzhiyun};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun&pcie0_phy {
362*4882a593Smuzhiyun	status = "okay";
363*4882a593Smuzhiyun};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun&pcie1_phy {
366*4882a593Smuzhiyun	status = "okay";
367*4882a593Smuzhiyun};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun&pwm {
370*4882a593Smuzhiyun	pinctrl-names = "default";
371*4882a593Smuzhiyun	pinctrl-0 = <&pwm_pins_a>;
372*4882a593Smuzhiyun	status = "okay";
373*4882a593Smuzhiyun};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun&spi0 {
376*4882a593Smuzhiyun	pinctrl-names = "default";
377*4882a593Smuzhiyun	pinctrl-0 = <&spi0_pins_a>;
378*4882a593Smuzhiyun	status = "okay";
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun&uart0 {
382*4882a593Smuzhiyun	pinctrl-names = "default";
383*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins_a>;
384*4882a593Smuzhiyun	status = "okay";
385*4882a593Smuzhiyun};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun&uart1 {
388*4882a593Smuzhiyun	pinctrl-names = "default";
389*4882a593Smuzhiyun	pinctrl-0 = <&uart1_pins_a>;
390*4882a593Smuzhiyun	status = "okay";
391*4882a593Smuzhiyun};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun&uart2 {
394*4882a593Smuzhiyun	pinctrl-names = "default";
395*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins_a>;
396*4882a593Smuzhiyun	status = "okay";
397*4882a593Smuzhiyun};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun&usb1 {
400*4882a593Smuzhiyun	vusb33-supply = <&reg_3p3v>;
401*4882a593Smuzhiyun	vbus-supply = <&reg_5v>;
402*4882a593Smuzhiyun	status = "okay";
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&usb2 {
406*4882a593Smuzhiyun	vusb33-supply = <&reg_3p3v>;
407*4882a593Smuzhiyun	vbus-supply = <&reg_5v>;
408*4882a593Smuzhiyun	status = "okay";
409*4882a593Smuzhiyun};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun&u3phy1 {
412*4882a593Smuzhiyun	status = "okay";
413*4882a593Smuzhiyun};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun&u3phy2 {
416*4882a593Smuzhiyun	status = "okay";
417*4882a593Smuzhiyun};
418