1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017-2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Sean Wang <sean.wang@mediatek.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "mt7623a.dtsi" 11*4882a593Smuzhiyun#include "mt6323.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "MediaTek MT7623A with NAND reference board"; 15*4882a593Smuzhiyun compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun aliases { 18*4882a593Smuzhiyun serial2 = &uart2; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun chosen { 22*4882a593Smuzhiyun stdout-path = "serial2:115200n8"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpus { 26*4882a593Smuzhiyun cpu@0 { 27*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cpu@1 { 31*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun cpu@2 { 35*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun cpu@3 { 39*4882a593Smuzhiyun proc-supply = <&mt6323_vproc_reg>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun gpio-keys { 44*4882a593Smuzhiyun compatible = "gpio-keys"; 45*4882a593Smuzhiyun pinctrl-names = "default"; 46*4882a593Smuzhiyun pinctrl-0 = <&key_pins_a>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun factory { 49*4882a593Smuzhiyun label = "factory"; 50*4882a593Smuzhiyun linux,code = <BTN_0>; 51*4882a593Smuzhiyun gpios = <&pio 256 GPIO_ACTIVE_LOW>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun wps { 55*4882a593Smuzhiyun label = "wps"; 56*4882a593Smuzhiyun linux,code = <KEY_WPS_BUTTON>; 57*4882a593Smuzhiyun gpios = <&pio 257 GPIO_ACTIVE_HIGH>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun memory@80000000 { 62*4882a593Smuzhiyun device_type = "memory"; 63*4882a593Smuzhiyun reg = <0 0x80000000 0 0x20000000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reg_1p8v: regulator-1p8v { 67*4882a593Smuzhiyun compatible = "regulator-fixed"; 68*4882a593Smuzhiyun regulator-name = "fixed-1.8V"; 69*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 70*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 71*4882a593Smuzhiyun regulator-boot-on; 72*4882a593Smuzhiyun regulator-always-on; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 76*4882a593Smuzhiyun compatible = "regulator-fixed"; 77*4882a593Smuzhiyun regulator-name = "fixed-3.3V"; 78*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 79*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 80*4882a593Smuzhiyun regulator-boot-on; 81*4882a593Smuzhiyun regulator-always-on; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun reg_5v: regulator-5v { 85*4882a593Smuzhiyun compatible = "regulator-fixed"; 86*4882a593Smuzhiyun regulator-name = "fixed-5V"; 87*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 88*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 89*4882a593Smuzhiyun regulator-boot-on; 90*4882a593Smuzhiyun regulator-always-on; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun sound { 94*4882a593Smuzhiyun compatible = "mediatek,mt2701-wm8960-machine"; 95*4882a593Smuzhiyun mediatek,platform = <&afe>; 96*4882a593Smuzhiyun audio-routing = 97*4882a593Smuzhiyun "Headphone", "HP_L", 98*4882a593Smuzhiyun "Headphone", "HP_R", 99*4882a593Smuzhiyun "LINPUT1", "AMIC", 100*4882a593Smuzhiyun "RINPUT1", "AMIC"; 101*4882a593Smuzhiyun mediatek,audio-codec = <&wm8960>; 102*4882a593Smuzhiyun pinctrl-names = "default"; 103*4882a593Smuzhiyun pinctrl-0 = <&i2s0_pins_a>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&bch { 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&btif { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&crypto { 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyunð { 120*4882a593Smuzhiyun status = "okay"; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun gmac0: mac@0 { 123*4882a593Smuzhiyun compatible = "mediatek,eth-mac"; 124*4882a593Smuzhiyun reg = <0>; 125*4882a593Smuzhiyun phy-mode = "trgmii"; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun fixed-link { 128*4882a593Smuzhiyun speed = <1000>; 129*4882a593Smuzhiyun full-duplex; 130*4882a593Smuzhiyun pause; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun mdio-bus { 135*4882a593Smuzhiyun #address-cells = <1>; 136*4882a593Smuzhiyun #size-cells = <0>; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun switch@0 { 139*4882a593Smuzhiyun compatible = "mediatek,mt7530"; 140*4882a593Smuzhiyun reg = <0>; 141*4882a593Smuzhiyun mediatek,mcm; 142*4882a593Smuzhiyun resets = <ðsys MT2701_ETHSYS_MCM_RST>; 143*4882a593Smuzhiyun reset-names = "mcm"; 144*4882a593Smuzhiyun core-supply = <&mt6323_vpa_reg>; 145*4882a593Smuzhiyun io-supply = <&mt6323_vemc3v3_reg>; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun ports { 148*4882a593Smuzhiyun #address-cells = <1>; 149*4882a593Smuzhiyun #size-cells = <0>; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun port@0 { 152*4882a593Smuzhiyun reg = <0>; 153*4882a593Smuzhiyun label = "lan0"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun port@1 { 157*4882a593Smuzhiyun reg = <1>; 158*4882a593Smuzhiyun label = "lan1"; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun port@2 { 162*4882a593Smuzhiyun reg = <2>; 163*4882a593Smuzhiyun label = "lan2"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun port@3 { 167*4882a593Smuzhiyun reg = <3>; 168*4882a593Smuzhiyun label = "lan3"; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun port@4 { 172*4882a593Smuzhiyun reg = <4>; 173*4882a593Smuzhiyun label = "wan"; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun port@6 { 177*4882a593Smuzhiyun reg = <6>; 178*4882a593Smuzhiyun label = "cpu"; 179*4882a593Smuzhiyun ethernet = <&gmac0>; 180*4882a593Smuzhiyun phy-mode = "trgmii"; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun fixed-link { 183*4882a593Smuzhiyun speed = <1000>; 184*4882a593Smuzhiyun full-duplex; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&i2c0 { 193*4882a593Smuzhiyun pinctrl-names = "default"; 194*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins_a>; 195*4882a593Smuzhiyun status = "okay"; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&i2c1 { 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins_b>; 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun wm8960: wm8960@1a { 204*4882a593Smuzhiyun compatible = "wlf,wm8960"; 205*4882a593Smuzhiyun reg = <0x1a>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&i2c2 { 210*4882a593Smuzhiyun pinctrl-names = "default"; 211*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins_b>; 212*4882a593Smuzhiyun status = "okay"; 213*4882a593Smuzhiyun}; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun&mmc1 { 216*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 217*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins_default>; 218*4882a593Smuzhiyun pinctrl-1 = <&mmc1_pins_uhs>; 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun bus-width = <4>; 221*4882a593Smuzhiyun max-frequency = <50000000>; 222*4882a593Smuzhiyun cap-sd-highspeed; 223*4882a593Smuzhiyun cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; 224*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 225*4882a593Smuzhiyun vqmmc-supply = <®_3p3v>; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&nandc { 229*4882a593Smuzhiyun pinctrl-names = "default"; 230*4882a593Smuzhiyun pinctrl-0 = <&nand_pins_default>; 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun nand@0 { 234*4882a593Smuzhiyun reg = <0>; 235*4882a593Smuzhiyun spare_per_sector = <64>; 236*4882a593Smuzhiyun nand-ecc-mode = "hw"; 237*4882a593Smuzhiyun nand-ecc-strength = <12>; 238*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun partitions { 241*4882a593Smuzhiyun compatible = "fixed-partitions"; 242*4882a593Smuzhiyun #address-cells = <1>; 243*4882a593Smuzhiyun #size-cells = <1>; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun partition@0 { 246*4882a593Smuzhiyun label = "preloader"; 247*4882a593Smuzhiyun reg = <0x0 0x40000>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun partition@40000 { 251*4882a593Smuzhiyun label = "uboot"; 252*4882a593Smuzhiyun reg = <0x40000 0x80000>; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun partition@c0000 { 256*4882a593Smuzhiyun label = "uboot-env"; 257*4882a593Smuzhiyun reg = <0xC0000 0x40000>; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun partition@140000 { 261*4882a593Smuzhiyun label = "bootimg"; 262*4882a593Smuzhiyun reg = <0x140000 0x2000000>; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun partition@2140000 { 266*4882a593Smuzhiyun label = "recovery"; 267*4882a593Smuzhiyun reg = <0x2140000 0x2000000>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun partition@4140000 { 271*4882a593Smuzhiyun label = "rootfs"; 272*4882a593Smuzhiyun reg = <0x4140000 0x1000000>; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun partition@5140000 { 276*4882a593Smuzhiyun label = "usrdata"; 277*4882a593Smuzhiyun reg = <0x5140000 0x1000000>; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&pcie { 284*4882a593Smuzhiyun pinctrl-names = "default"; 285*4882a593Smuzhiyun pinctrl-0 = <&pcie_default>; 286*4882a593Smuzhiyun status = "okay"; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun pcie@0,0 { 289*4882a593Smuzhiyun status = "okay"; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun pcie@1,0 { 293*4882a593Smuzhiyun status = "okay"; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun}; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun&pcie0_phy { 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&pcie1_phy { 302*4882a593Smuzhiyun status = "okay"; 303*4882a593Smuzhiyun}; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun&pwm { 306*4882a593Smuzhiyun pinctrl-names = "default"; 307*4882a593Smuzhiyun pinctrl-0 = <&pwm_pins_a>; 308*4882a593Smuzhiyun status = "okay"; 309*4882a593Smuzhiyun}; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun&spi0 { 312*4882a593Smuzhiyun pinctrl-names = "default"; 313*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins_a>; 314*4882a593Smuzhiyun status = "okay"; 315*4882a593Smuzhiyun}; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun&spi1 { 318*4882a593Smuzhiyun pinctrl-names = "default"; 319*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins_a>; 320*4882a593Smuzhiyun status = "okay"; 321*4882a593Smuzhiyun}; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun&uart2 { 324*4882a593Smuzhiyun pinctrl-names = "default"; 325*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins_b>; 326*4882a593Smuzhiyun status = "okay"; 327*4882a593Smuzhiyun}; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun&usb1 { 330*4882a593Smuzhiyun vusb33-supply = <®_3p3v>; 331*4882a593Smuzhiyun vbus-supply = <®_5v>; 332*4882a593Smuzhiyun status = "okay"; 333*4882a593Smuzhiyun}; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun&u3phy1 { 336*4882a593Smuzhiyun status = "okay"; 337*4882a593Smuzhiyun}; 338