1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2014 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Howard Chen <ibanezchen@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun compatible = "mediatek,mt6592"; 15*4882a593Smuzhiyun interrupt-parent = <&sysirq>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@0 { 22*4882a593Smuzhiyun device_type = "cpu"; 23*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 24*4882a593Smuzhiyun reg = <0x0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun cpu@1 { 27*4882a593Smuzhiyun device_type = "cpu"; 28*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 29*4882a593Smuzhiyun reg = <0x1>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun cpu@2 { 32*4882a593Smuzhiyun device_type = "cpu"; 33*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 34*4882a593Smuzhiyun reg = <0x2>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun cpu@3 { 37*4882a593Smuzhiyun device_type = "cpu"; 38*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 39*4882a593Smuzhiyun reg = <0x3>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun cpu@4 { 42*4882a593Smuzhiyun device_type = "cpu"; 43*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 44*4882a593Smuzhiyun reg = <0x4>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun cpu@5 { 47*4882a593Smuzhiyun device_type = "cpu"; 48*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 49*4882a593Smuzhiyun reg = <0x5>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun cpu@6 { 52*4882a593Smuzhiyun device_type = "cpu"; 53*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 54*4882a593Smuzhiyun reg = <0x6>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun cpu@7 { 57*4882a593Smuzhiyun device_type = "cpu"; 58*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 59*4882a593Smuzhiyun reg = <0x7>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun system_clk: dummy13m { 64*4882a593Smuzhiyun compatible = "fixed-clock"; 65*4882a593Smuzhiyun clock-frequency = <13000000>; 66*4882a593Smuzhiyun #clock-cells = <0>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun rtc_clk: dummy32k { 70*4882a593Smuzhiyun compatible = "fixed-clock"; 71*4882a593Smuzhiyun clock-frequency = <32000>; 72*4882a593Smuzhiyun #clock-cells = <0>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun uart_clk: dummy26m { 76*4882a593Smuzhiyun compatible = "fixed-clock"; 77*4882a593Smuzhiyun clock-frequency = <26000000>; 78*4882a593Smuzhiyun #clock-cells = <0>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun timer: timer@10008000 { 82*4882a593Smuzhiyun compatible = "mediatek,mt6577-timer"; 83*4882a593Smuzhiyun reg = <0x10008000 0x80>; 84*4882a593Smuzhiyun interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 85*4882a593Smuzhiyun clocks = <&system_clk>, <&rtc_clk>; 86*4882a593Smuzhiyun clock-names = "system-clk", "rtc-clk"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun sysirq: interrupt-controller@10200220 { 90*4882a593Smuzhiyun compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; 91*4882a593Smuzhiyun interrupt-controller; 92*4882a593Smuzhiyun #interrupt-cells = <3>; 93*4882a593Smuzhiyun interrupt-parent = <&gic>; 94*4882a593Smuzhiyun reg = <0x10200220 0x1c>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun gic: interrupt-controller@10211000 { 98*4882a593Smuzhiyun compatible = "arm,cortex-a7-gic"; 99*4882a593Smuzhiyun interrupt-controller; 100*4882a593Smuzhiyun #interrupt-cells = <3>; 101*4882a593Smuzhiyun interrupt-parent = <&gic>; 102*4882a593Smuzhiyun reg = <0x10211000 0x1000>, 103*4882a593Smuzhiyun <0x10212000 0x1000>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun uart0: serial@11002000 { 107*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 108*4882a593Smuzhiyun reg = <0x11002000 0x400>; 109*4882a593Smuzhiyun interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 110*4882a593Smuzhiyun clocks = <&uart_clk>; 111*4882a593Smuzhiyun status = "disabled"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun uart1: serial@11003000 { 115*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 116*4882a593Smuzhiyun reg = <0x11003000 0x400>; 117*4882a593Smuzhiyun interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 118*4882a593Smuzhiyun clocks = <&uart_clk>; 119*4882a593Smuzhiyun status = "disabled"; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun uart2: serial@11004000 { 123*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 124*4882a593Smuzhiyun reg = <0x11004000 0x400>; 125*4882a593Smuzhiyun interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 126*4882a593Smuzhiyun clocks = <&uart_clk>; 127*4882a593Smuzhiyun status = "disabled"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun uart3: serial@11005000 { 131*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 132*4882a593Smuzhiyun reg = <0x11005000 0x400>; 133*4882a593Smuzhiyun interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 134*4882a593Smuzhiyun clocks = <&uart_clk>; 135*4882a593Smuzhiyun status = "disabled"; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun}; 138