1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2014 MundoReader S.L. 4*4882a593Smuzhiyun * Author: Matthias Brugger <matthias.bgg@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun*/ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun compatible = "mediatek,mt6589"; 15*4882a593Smuzhiyun interrupt-parent = <&sysirq>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpu@0 { 22*4882a593Smuzhiyun device_type = "cpu"; 23*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 24*4882a593Smuzhiyun reg = <0x0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun cpu@1 { 27*4882a593Smuzhiyun device_type = "cpu"; 28*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 29*4882a593Smuzhiyun reg = <0x1>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun cpu@2 { 32*4882a593Smuzhiyun device_type = "cpu"; 33*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 34*4882a593Smuzhiyun reg = <0x2>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun cpu@3 { 37*4882a593Smuzhiyun device_type = "cpu"; 38*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 39*4882a593Smuzhiyun reg = <0x3>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun clocks { 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <1>; 47*4882a593Smuzhiyun compatible = "simple-bus"; 48*4882a593Smuzhiyun ranges; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun system_clk: dummy13m { 51*4882a593Smuzhiyun compatible = "fixed-clock"; 52*4882a593Smuzhiyun clock-frequency = <13000000>; 53*4882a593Smuzhiyun #clock-cells = <0>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun rtc_clk: dummy32k { 57*4882a593Smuzhiyun compatible = "fixed-clock"; 58*4882a593Smuzhiyun clock-frequency = <32000>; 59*4882a593Smuzhiyun #clock-cells = <0>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun uart_clk: dummy26m { 63*4882a593Smuzhiyun compatible = "fixed-clock"; 64*4882a593Smuzhiyun clock-frequency = <26000000>; 65*4882a593Smuzhiyun #clock-cells = <0>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun soc { 70*4882a593Smuzhiyun #address-cells = <1>; 71*4882a593Smuzhiyun #size-cells = <1>; 72*4882a593Smuzhiyun compatible = "simple-bus"; 73*4882a593Smuzhiyun ranges; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun timer: timer@10008000 { 76*4882a593Smuzhiyun compatible = "mediatek,mt6577-timer"; 77*4882a593Smuzhiyun reg = <0x10008000 0x80>; 78*4882a593Smuzhiyun interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; 79*4882a593Smuzhiyun clocks = <&system_clk>, <&rtc_clk>; 80*4882a593Smuzhiyun clock-names = "system-clk", "rtc-clk"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun sysirq: interrupt-controller@10200100 { 84*4882a593Smuzhiyun compatible = "mediatek,mt6589-sysirq", 85*4882a593Smuzhiyun "mediatek,mt6577-sysirq"; 86*4882a593Smuzhiyun interrupt-controller; 87*4882a593Smuzhiyun #interrupt-cells = <3>; 88*4882a593Smuzhiyun interrupt-parent = <&gic>; 89*4882a593Smuzhiyun reg = <0x10200100 0x1c>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun gic: interrupt-controller@10211000 { 93*4882a593Smuzhiyun compatible = "arm,cortex-a7-gic"; 94*4882a593Smuzhiyun interrupt-controller; 95*4882a593Smuzhiyun #interrupt-cells = <3>; 96*4882a593Smuzhiyun interrupt-parent = <&gic>; 97*4882a593Smuzhiyun reg = <0x10211000 0x1000>, 98*4882a593Smuzhiyun <0x10212000 0x2000>, 99*4882a593Smuzhiyun <0x10214000 0x2000>, 100*4882a593Smuzhiyun <0x10216000 0x2000>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun uart0: serial@11006000 { 104*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 105*4882a593Smuzhiyun reg = <0x11006000 0x400>; 106*4882a593Smuzhiyun interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 107*4882a593Smuzhiyun clocks = <&uart_clk>; 108*4882a593Smuzhiyun status = "disabled"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun uart1: serial@11007000 { 112*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 113*4882a593Smuzhiyun reg = <0x11007000 0x400>; 114*4882a593Smuzhiyun interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 115*4882a593Smuzhiyun clocks = <&uart_clk>; 116*4882a593Smuzhiyun status = "disabled"; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun uart2: serial@11008000 { 120*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 121*4882a593Smuzhiyun reg = <0x11008000 0x400>; 122*4882a593Smuzhiyun interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 123*4882a593Smuzhiyun clocks = <&uart_clk>; 124*4882a593Smuzhiyun status = "disabled"; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun uart3: serial@11009000 { 128*4882a593Smuzhiyun compatible = "mediatek,mt6577-uart"; 129*4882a593Smuzhiyun reg = <0x11009000 0x400>; 130*4882a593Smuzhiyun interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 131*4882a593Smuzhiyun clocks = <&uart_clk>; 132*4882a593Smuzhiyun status = "disabled"; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun wdt: watchdog@10000000 { 136*4882a593Smuzhiyun compatible = "mediatek,mt6589-wdt"; 137*4882a593Smuzhiyun reg = <0x10000000 0x44>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun}; 141