1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Biao Huang <biao.huang@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DTS_MT2701_PINFUNC_H 8*4882a593Smuzhiyun #define __DTS_MT2701_PINFUNC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <dt-bindings/pinctrl/mt65xx.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) 13*4882a593Smuzhiyun #define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) 14*4882a593Smuzhiyun #define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) 17*4882a593Smuzhiyun #define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) 18*4882a593Smuzhiyun #define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) 21*4882a593Smuzhiyun #define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) 24*4882a593Smuzhiyun #define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) 27*4882a593Smuzhiyun #define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) 30*4882a593Smuzhiyun #define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) 31*4882a593Smuzhiyun #define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) 34*4882a593Smuzhiyun #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) 35*4882a593Smuzhiyun #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) 36*4882a593Smuzhiyun #define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) 39*4882a593Smuzhiyun #define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) 40*4882a593Smuzhiyun #define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4) 41*4882a593Smuzhiyun #define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) 44*4882a593Smuzhiyun #define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) 45*4882a593Smuzhiyun #define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) 46*4882a593Smuzhiyun #define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4) 47*4882a593Smuzhiyun #define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) 50*4882a593Smuzhiyun #define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) 51*4882a593Smuzhiyun #define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) 52*4882a593Smuzhiyun #define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) 53*4882a593Smuzhiyun #define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4) 54*4882a593Smuzhiyun #define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) 57*4882a593Smuzhiyun #define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) 60*4882a593Smuzhiyun #define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) 63*4882a593Smuzhiyun #define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) 66*4882a593Smuzhiyun #define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) 69*4882a593Smuzhiyun #define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) 70*4882a593Smuzhiyun #define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2) 71*4882a593Smuzhiyun #define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) 72*4882a593Smuzhiyun #define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) 75*4882a593Smuzhiyun #define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) 76*4882a593Smuzhiyun #define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2) 77*4882a593Smuzhiyun #define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) 80*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) 81*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) 82*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) 83*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) 84*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6) 85*4882a593Smuzhiyun #define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) 88*4882a593Smuzhiyun #define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) 89*4882a593Smuzhiyun #define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) 90*4882a593Smuzhiyun #define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) 91*4882a593Smuzhiyun #define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6) 92*4882a593Smuzhiyun #define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) 95*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) 96*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2) 97*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3) 98*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) 99*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) 100*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6) 101*4882a593Smuzhiyun #define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) 104*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) 105*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2) 106*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3) 107*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) 108*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) 109*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6) 110*4882a593Smuzhiyun #define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) 113*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1) 114*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3) 115*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) 116*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) 117*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7) 118*4882a593Smuzhiyun #define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) 121*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1) 122*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3) 123*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) 124*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) 125*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7) 126*4882a593Smuzhiyun #define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) 129*4882a593Smuzhiyun #define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1) 130*4882a593Smuzhiyun #define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3) 131*4882a593Smuzhiyun #define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) 132*4882a593Smuzhiyun #define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7) 133*4882a593Smuzhiyun #define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) 136*4882a593Smuzhiyun #define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1) 137*4882a593Smuzhiyun #define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3) 138*4882a593Smuzhiyun #define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) 139*4882a593Smuzhiyun #define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) 142*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1) 143*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) 144*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3) 145*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) 146*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) 147*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) 148*4882a593Smuzhiyun #define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) 151*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1) 152*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) 153*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3) 154*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) 155*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) 156*4882a593Smuzhiyun #define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) 159*4882a593Smuzhiyun #define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) 160*4882a593Smuzhiyun #define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3) 161*4882a593Smuzhiyun #define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) 162*4882a593Smuzhiyun #define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) 163*4882a593Smuzhiyun #define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7) 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) 166*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1) 167*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) 168*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3) 169*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) 170*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) 171*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7) 172*4882a593Smuzhiyun #define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) 175*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) 176*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) 177*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3) 178*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) 179*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) 180*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6) 181*4882a593Smuzhiyun #define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7) 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) 184*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) 185*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3) 186*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) 187*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) 188*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6) 189*4882a593Smuzhiyun #define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) 192*4882a593Smuzhiyun #define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) 193*4882a593Smuzhiyun #define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) 194*4882a593Smuzhiyun #define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) 195*4882a593Smuzhiyun #define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6) 196*4882a593Smuzhiyun #define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7) 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun #define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) 199*4882a593Smuzhiyun #define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) 200*4882a593Smuzhiyun #define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) 201*4882a593Smuzhiyun #define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) 202*4882a593Smuzhiyun #define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6) 203*4882a593Smuzhiyun #define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7) 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) 206*4882a593Smuzhiyun #define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) 207*4882a593Smuzhiyun #define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) 208*4882a593Smuzhiyun #define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) 211*4882a593Smuzhiyun #define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) 212*4882a593Smuzhiyun #define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) 213*4882a593Smuzhiyun #define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) 214*4882a593Smuzhiyun #define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) 217*4882a593Smuzhiyun #define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) 218*4882a593Smuzhiyun #define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) 219*4882a593Smuzhiyun #define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) 220*4882a593Smuzhiyun #define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) 223*4882a593Smuzhiyun #define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) 224*4882a593Smuzhiyun #define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) 225*4882a593Smuzhiyun #define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) 228*4882a593Smuzhiyun #define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) 229*4882a593Smuzhiyun #define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) 230*4882a593Smuzhiyun #define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) 233*4882a593Smuzhiyun #define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1) 234*4882a593Smuzhiyun #define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) 237*4882a593Smuzhiyun #define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1) 238*4882a593Smuzhiyun #define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) 241*4882a593Smuzhiyun #define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1) 242*4882a593Smuzhiyun #define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) 245*4882a593Smuzhiyun #define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) 248*4882a593Smuzhiyun #define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1) 249*4882a593Smuzhiyun #define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) 252*4882a593Smuzhiyun #define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1) 253*4882a593Smuzhiyun #define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) 256*4882a593Smuzhiyun #define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) 257*4882a593Smuzhiyun #define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) 258*4882a593Smuzhiyun #define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3) 259*4882a593Smuzhiyun #define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6) 260*4882a593Smuzhiyun #define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) 263*4882a593Smuzhiyun #define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) 264*4882a593Smuzhiyun #define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3) 265*4882a593Smuzhiyun #define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) 266*4882a593Smuzhiyun #define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5) 267*4882a593Smuzhiyun #define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7) 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun #define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) 270*4882a593Smuzhiyun #define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) 271*4882a593Smuzhiyun #define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) 272*4882a593Smuzhiyun #define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) 273*4882a593Smuzhiyun #define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) 276*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) 277*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) 278*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) 279*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) 280*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5) 281*4882a593Smuzhiyun #define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7) 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun #define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) 284*4882a593Smuzhiyun #define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) 285*4882a593Smuzhiyun #define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) 286*4882a593Smuzhiyun #define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) 287*4882a593Smuzhiyun #define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7) 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) 290*4882a593Smuzhiyun #define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun #define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) 293*4882a593Smuzhiyun #define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) 296*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) 297*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3) 298*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4) 299*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) 300*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6) 301*4882a593Smuzhiyun #define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7) 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun #define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) 304*4882a593Smuzhiyun #define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) 305*4882a593Smuzhiyun #define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) 306*4882a593Smuzhiyun #define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6) 307*4882a593Smuzhiyun #define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7) 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun #define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) 310*4882a593Smuzhiyun #define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) 311*4882a593Smuzhiyun #define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) 312*4882a593Smuzhiyun #define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6) 313*4882a593Smuzhiyun #define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7) 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) 316*4882a593Smuzhiyun #define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun #define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) 319*4882a593Smuzhiyun #define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun #define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) 322*4882a593Smuzhiyun #define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun #define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) 325*4882a593Smuzhiyun #define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun #define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) 328*4882a593Smuzhiyun #define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) 329*4882a593Smuzhiyun #define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) 330*4882a593Smuzhiyun #define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun #define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) 333*4882a593Smuzhiyun #define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) 334*4882a593Smuzhiyun #define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) 337*4882a593Smuzhiyun #define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) 338*4882a593Smuzhiyun #define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun #define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) 341*4882a593Smuzhiyun #define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) 342*4882a593Smuzhiyun #define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) 345*4882a593Smuzhiyun #define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) 346*4882a593Smuzhiyun #define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) 347*4882a593Smuzhiyun #define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7) 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun #define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) 350*4882a593Smuzhiyun #define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) 351*4882a593Smuzhiyun #define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7) 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) 354*4882a593Smuzhiyun #define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) 357*4882a593Smuzhiyun #define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) 360*4882a593Smuzhiyun #define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun #define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) 363*4882a593Smuzhiyun #define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun #define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) 366*4882a593Smuzhiyun #define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun #define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) 369*4882a593Smuzhiyun #define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun #define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) 372*4882a593Smuzhiyun #define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) 375*4882a593Smuzhiyun #define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun #define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) 378*4882a593Smuzhiyun #define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) 381*4882a593Smuzhiyun #define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun #define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) 384*4882a593Smuzhiyun #define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) 385*4882a593Smuzhiyun #define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3) 386*4882a593Smuzhiyun #define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4) 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) 389*4882a593Smuzhiyun #define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) 390*4882a593Smuzhiyun #define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) 391*4882a593Smuzhiyun #define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3) 392*4882a593Smuzhiyun #define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4) 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun #define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) 395*4882a593Smuzhiyun #define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) 396*4882a593Smuzhiyun #define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) 397*4882a593Smuzhiyun #define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3) 398*4882a593Smuzhiyun #define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4) 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun #define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) 401*4882a593Smuzhiyun #define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) 402*4882a593Smuzhiyun #define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3) 403*4882a593Smuzhiyun #define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4) 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun #define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) 406*4882a593Smuzhiyun #define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) 407*4882a593Smuzhiyun #define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2) 408*4882a593Smuzhiyun #define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3) 409*4882a593Smuzhiyun #define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) 410*4882a593Smuzhiyun #define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7) 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) 413*4882a593Smuzhiyun #define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) 414*4882a593Smuzhiyun #define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2) 415*4882a593Smuzhiyun #define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3) 416*4882a593Smuzhiyun #define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) 417*4882a593Smuzhiyun #define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7) 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun #define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) 420*4882a593Smuzhiyun #define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) 421*4882a593Smuzhiyun #define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2) 422*4882a593Smuzhiyun #define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5) 423*4882a593Smuzhiyun #define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) 424*4882a593Smuzhiyun #define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7) 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) 427*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) 428*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2) 429*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3) 430*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5) 431*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6) 432*4882a593Smuzhiyun #define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7) 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) 435*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) 436*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2) 437*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3) 438*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5) 439*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6) 440*4882a593Smuzhiyun #define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7) 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) 443*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) 444*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2) 445*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3) 446*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4) 447*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5) 448*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6) 449*4882a593Smuzhiyun #define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7) 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun #define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) 452*4882a593Smuzhiyun #define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) 453*4882a593Smuzhiyun #define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4) 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) 456*4882a593Smuzhiyun #define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) 457*4882a593Smuzhiyun #define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4) 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun #define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) 460*4882a593Smuzhiyun #define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) 461*4882a593Smuzhiyun #define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4) 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) 464*4882a593Smuzhiyun #define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) 465*4882a593Smuzhiyun #define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4) 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun #define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) 468*4882a593Smuzhiyun #define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) 469*4882a593Smuzhiyun #define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4) 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun #define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) 472*4882a593Smuzhiyun #define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) 473*4882a593Smuzhiyun #define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4) 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun #define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) 476*4882a593Smuzhiyun #define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) 477*4882a593Smuzhiyun #define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4) 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun #define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) 480*4882a593Smuzhiyun #define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) 481*4882a593Smuzhiyun #define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4) 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) 484*4882a593Smuzhiyun #define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) 485*4882a593Smuzhiyun #define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4) 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun #define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) 488*4882a593Smuzhiyun #define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) 489*4882a593Smuzhiyun #define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4) 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun #define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) 492*4882a593Smuzhiyun #define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) 493*4882a593Smuzhiyun #define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4) 494*4882a593Smuzhiyun #define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun #define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) 497*4882a593Smuzhiyun #define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1) 498*4882a593Smuzhiyun #define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4) 499*4882a593Smuzhiyun #define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5) 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun #define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) 502*4882a593Smuzhiyun #define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1) 503*4882a593Smuzhiyun #define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4) 504*4882a593Smuzhiyun #define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5) 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun #define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) 507*4882a593Smuzhiyun #define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1) 508*4882a593Smuzhiyun #define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4) 509*4882a593Smuzhiyun #define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5) 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun #define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) 512*4882a593Smuzhiyun #define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1) 513*4882a593Smuzhiyun #define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4) 514*4882a593Smuzhiyun #define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5) 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun #define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) 517*4882a593Smuzhiyun #define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) 518*4882a593Smuzhiyun #define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6) 519*4882a593Smuzhiyun #define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7) 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun #define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) 522*4882a593Smuzhiyun #define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) 523*4882a593Smuzhiyun #define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3) 524*4882a593Smuzhiyun #define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4) 525*4882a593Smuzhiyun #define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7) 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun #define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) 528*4882a593Smuzhiyun #define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1) 529*4882a593Smuzhiyun #define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5) 530*4882a593Smuzhiyun #define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6) 531*4882a593Smuzhiyun #define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7) 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun #define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) 534*4882a593Smuzhiyun #define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1) 535*4882a593Smuzhiyun #define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5) 536*4882a593Smuzhiyun #define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6) 537*4882a593Smuzhiyun #define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7) 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun #define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) 540*4882a593Smuzhiyun #define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1) 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun #define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) 543*4882a593Smuzhiyun #define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1) 544*4882a593Smuzhiyun #define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) 545*4882a593Smuzhiyun #define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5) 546*4882a593Smuzhiyun #define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7) 547*4882a593Smuzhiyun #define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9) 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun #define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) 550*4882a593Smuzhiyun #define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1) 551*4882a593Smuzhiyun #define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2) 552*4882a593Smuzhiyun #define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5) 553*4882a593Smuzhiyun #define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7) 554*4882a593Smuzhiyun #define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9) 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun #define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) 557*4882a593Smuzhiyun #define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1) 558*4882a593Smuzhiyun #define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2) 559*4882a593Smuzhiyun #define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5) 560*4882a593Smuzhiyun #define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7) 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun #define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) 563*4882a593Smuzhiyun #define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1) 564*4882a593Smuzhiyun #define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2) 565*4882a593Smuzhiyun #define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3) 566*4882a593Smuzhiyun #define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5) 567*4882a593Smuzhiyun #define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7) 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun #define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) 570*4882a593Smuzhiyun #define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1) 571*4882a593Smuzhiyun #define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2) 572*4882a593Smuzhiyun #define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3) 573*4882a593Smuzhiyun #define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5) 574*4882a593Smuzhiyun #define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7) 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) 577*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) 578*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2) 579*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4) 580*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) 581*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7) 582*4882a593Smuzhiyun #define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11) 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) 585*4882a593Smuzhiyun #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) 586*4882a593Smuzhiyun #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) 587*4882a593Smuzhiyun #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5) 588*4882a593Smuzhiyun #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7) 589*4882a593Smuzhiyun #define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11) 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun #define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) 592*4882a593Smuzhiyun #define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) 593*4882a593Smuzhiyun #define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2) 594*4882a593Smuzhiyun #define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7) 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) 597*4882a593Smuzhiyun #define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) 598*4882a593Smuzhiyun #define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun #define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) 601*4882a593Smuzhiyun #define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) 602*4882a593Smuzhiyun #define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2) 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun #define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) 605*4882a593Smuzhiyun #define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) 606*4882a593Smuzhiyun #define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2) 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun #define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) 609*4882a593Smuzhiyun #define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun #define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) 612*4882a593Smuzhiyun #define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun #define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) 615*4882a593Smuzhiyun #define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1) 616*4882a593Smuzhiyun #define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2) 617*4882a593Smuzhiyun #define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3) 618*4882a593Smuzhiyun #define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4) 619*4882a593Smuzhiyun #define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7) 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun #define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) 622*4882a593Smuzhiyun #define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1) 623*4882a593Smuzhiyun #define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2) 624*4882a593Smuzhiyun #define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3) 625*4882a593Smuzhiyun #define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4) 626*4882a593Smuzhiyun #define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7) 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun #define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) 629*4882a593Smuzhiyun #define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1) 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun #define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) 632*4882a593Smuzhiyun #define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1) 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun #define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun #define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) 637*4882a593Smuzhiyun #define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1) 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun #define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) 640*4882a593Smuzhiyun #define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1) 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun #define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9) 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun #define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9) 645*4882a593Smuzhiyun #define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14) 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun #define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9) 648*4882a593Smuzhiyun #define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14) 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun #define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9) 651*4882a593Smuzhiyun #define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14) 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun #define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9) 654*4882a593Smuzhiyun #define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14) 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun #define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9) 657*4882a593Smuzhiyun #define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14) 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun #define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9) 660*4882a593Smuzhiyun #define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14) 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun #define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9) 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun #define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9) 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9) 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun #define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9) 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun #define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9) 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun #define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) 673*4882a593Smuzhiyun #define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) 674*4882a593Smuzhiyun #define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7) 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun #define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) 677*4882a593Smuzhiyun #define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun #define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) 680*4882a593Smuzhiyun #define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) 681*4882a593Smuzhiyun #define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6) 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun #define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) 684*4882a593Smuzhiyun #define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) 685*4882a593Smuzhiyun #define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6) 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun #define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) 688*4882a593Smuzhiyun #define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) 689*4882a593Smuzhiyun #define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6) 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun #define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) 692*4882a593Smuzhiyun #define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) 693*4882a593Smuzhiyun #define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6) 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun #define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) 696*4882a593Smuzhiyun #define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1) 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun #define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) 699*4882a593Smuzhiyun #define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1) 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun #define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) 702*4882a593Smuzhiyun #define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun #define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) 705*4882a593Smuzhiyun #define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun #define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0) 708*4882a593Smuzhiyun #define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun #define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0) 711*4882a593Smuzhiyun #define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun #define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0) 714*4882a593Smuzhiyun #define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun #define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0) 717*4882a593Smuzhiyun #define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1) 718*4882a593Smuzhiyun #define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6) 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun #define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0) 721*4882a593Smuzhiyun #define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1) 722*4882a593Smuzhiyun #define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6) 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun #define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0) 725*4882a593Smuzhiyun #define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun #endif /* __DTS_MT2701_PINFUNC_H */ 728