1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 3*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 4*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 5*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun compatible = "socionext,sc2000a"; 9*4882a593Smuzhiyun interrupt-parent = <&gic>; 10*4882a593Smuzhiyun #address-cells = <1>; 11*4882a593Smuzhiyun #size-cells = <1>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <0>; 16*4882a593Smuzhiyun enable-method = "socionext,milbeaut-m10v-smp"; 17*4882a593Smuzhiyun cpu@f00 { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 20*4882a593Smuzhiyun reg = <0xf00>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun cpu@f01 { 23*4882a593Smuzhiyun device_type = "cpu"; 24*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 25*4882a593Smuzhiyun reg = <0xf01>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun cpu@f02 { 28*4882a593Smuzhiyun device_type = "cpu"; 29*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 30*4882a593Smuzhiyun reg = <0xf02>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun cpu@f03 { 33*4882a593Smuzhiyun device_type = "cpu"; 34*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 35*4882a593Smuzhiyun reg = <0xf03>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun timer { /* The Generic Timer */ 40*4882a593Smuzhiyun compatible = "arm,armv7-timer"; 41*4882a593Smuzhiyun interrupts = <GIC_PPI 13 42*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 43*4882a593Smuzhiyun <GIC_PPI 14 44*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 45*4882a593Smuzhiyun <GIC_PPI 11 46*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 47*4882a593Smuzhiyun <GIC_PPI 10 48*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 49*4882a593Smuzhiyun clock-frequency = <40000000>; 50*4882a593Smuzhiyun always-on; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun soc { 54*4882a593Smuzhiyun compatible = "simple-bus"; 55*4882a593Smuzhiyun #address-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <1>; 57*4882a593Smuzhiyun ranges; 58*4882a593Smuzhiyun interrupt-parent = <&gic>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun gic: interrupt-controller@1d000000 { 61*4882a593Smuzhiyun compatible = "arm,cortex-a7-gic"; 62*4882a593Smuzhiyun interrupt-controller; 63*4882a593Smuzhiyun #interrupt-cells = <3>; 64*4882a593Smuzhiyun reg = <0x1d001000 0x1000>, 65*4882a593Smuzhiyun <0x1d002000 0x1000>; /* CPU I/f base and size */ 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun timer@1e000050 { /* 32-bit Reload Timers */ 69*4882a593Smuzhiyun compatible = "socionext,milbeaut-timer"; 70*4882a593Smuzhiyun reg = <0x1e000050 0x20>; 71*4882a593Smuzhiyun interrupts = <0 91 4>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun uart1: serial@1e700010 { /* PE4, PE5 */ 75*4882a593Smuzhiyun /* Enable this as ttyUSI0 */ 76*4882a593Smuzhiyun compatible = "socionext,milbeaut-usio-uart"; 77*4882a593Smuzhiyun reg = <0x1e700010 0x10>; 78*4882a593Smuzhiyun interrupts = <0 141 0x4>, <0 149 0x4>; 79*4882a593Smuzhiyun interrupt-names = "rx", "tx"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun sram@0 { 85*4882a593Smuzhiyun compatible = "mmio-sram"; 86*4882a593Smuzhiyun reg = <0x0 0x10000>; 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <1>; 89*4882a593Smuzhiyun ranges = <0 0x0 0x10000>; 90*4882a593Smuzhiyun smp-sram@f100 { 91*4882a593Smuzhiyun compatible = "socionext,milbeaut-smp-sram"; 92*4882a593Smuzhiyun reg = <0xf100 0x20>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun}; 96