1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "lpc18xx.dtsi" 11*4882a593Smuzhiyun#include "lpc4357.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "MYIR Tech LPC4357 Development Board"; 17*4882a593Smuzhiyun compatible = "myir,myd-lpc4357", "nxp,lpc4357"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun stdout-path = "serial3:115200n8"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun memory@28000000 { 24*4882a593Smuzhiyun device_type = "memory"; 25*4882a593Smuzhiyun reg = <0x28000000 0x2000000>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun leds { 29*4882a593Smuzhiyun compatible = "gpio-leds"; 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun pinctrl-0 = <&led_pins>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun led1 { 34*4882a593Smuzhiyun gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; 35*4882a593Smuzhiyun default-state = "off"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun led2 { 39*4882a593Smuzhiyun gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; 40*4882a593Smuzhiyun default-state = "off"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun led3 { 44*4882a593Smuzhiyun gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; 45*4882a593Smuzhiyun default-state = "off"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun led4 { 49*4882a593Smuzhiyun gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; 50*4882a593Smuzhiyun default-state = "off"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun led5 { 54*4882a593Smuzhiyun gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; 55*4882a593Smuzhiyun default-state = "off"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun led6 { 59*4882a593Smuzhiyun gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; 60*4882a593Smuzhiyun default-state = "off"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun panel: panel { 65*4882a593Smuzhiyun compatible = "innolux,at070tn92"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun port { 68*4882a593Smuzhiyun panel_input: endpoint { 69*4882a593Smuzhiyun remote-endpoint = <&lcdc_output>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun vcc: vcc_fixed { 75*4882a593Smuzhiyun compatible = "regulator-fixed"; 76*4882a593Smuzhiyun regulator-name = "vcc-supply"; 77*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 78*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun vmmc: vmmc_fixed { 82*4882a593Smuzhiyun compatible = "regulator-fixed"; 83*4882a593Smuzhiyun regulator-name = "vmmc-supply"; 84*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 85*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&pinctrl { 90*4882a593Smuzhiyun can0_pins: can0-pins { 91*4882a593Smuzhiyun can_rd_cfg { 92*4882a593Smuzhiyun pins = "p3_1"; 93*4882a593Smuzhiyun function = "can0"; 94*4882a593Smuzhiyun input-enable; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun can_td_cfg { 98*4882a593Smuzhiyun pins = "p3_2"; 99*4882a593Smuzhiyun function = "can0"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun can1_pins: can1-pins { 104*4882a593Smuzhiyun can_rd_cfg { 105*4882a593Smuzhiyun pins = "pe_1"; 106*4882a593Smuzhiyun function = "can1"; 107*4882a593Smuzhiyun input-enable; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun can_td_cfg { 111*4882a593Smuzhiyun pins = "pe_0"; 112*4882a593Smuzhiyun function = "can1"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun emc_pins: emc-pins { 117*4882a593Smuzhiyun emc_addr0_22_cfg { 118*4882a593Smuzhiyun pins = "p2_9", "p2_10", "p2_11", "p2_12", 119*4882a593Smuzhiyun "p2_13", "p1_0", "p1_1", "p1_2", 120*4882a593Smuzhiyun "p2_8", "p2_7", "p2_6", "p2_2", 121*4882a593Smuzhiyun "p2_1", "p2_0", "p6_8", "p6_7", 122*4882a593Smuzhiyun "pd_16", "pd_15", "pe_0", "pe_1", 123*4882a593Smuzhiyun "pe_2", "pe_3", "pe_4"; 124*4882a593Smuzhiyun function = "emc"; 125*4882a593Smuzhiyun slew-rate = <1>; 126*4882a593Smuzhiyun bias-disable; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun emc_data0_15_cfg { 130*4882a593Smuzhiyun pins = "p1_7", "p1_8", "p1_9", "p1_10", 131*4882a593Smuzhiyun "p1_11", "p1_12", "p1_13", "p1_14", 132*4882a593Smuzhiyun "p5_4", "p5_5", "p5_6", "p5_7", 133*4882a593Smuzhiyun "p5_0", "p5_1", "p5_2", "p5_3"; 134*4882a593Smuzhiyun function = "emc"; 135*4882a593Smuzhiyun input-enable; 136*4882a593Smuzhiyun input-schmitt-disable; 137*4882a593Smuzhiyun slew-rate = <1>; 138*4882a593Smuzhiyun bias-disable; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun emc_we_oe_cfg { 142*4882a593Smuzhiyun pins = "p1_6", "p1_3"; 143*4882a593Smuzhiyun function = "emc"; 144*4882a593Smuzhiyun slew-rate = <1>; 145*4882a593Smuzhiyun bias-disable; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun emc_cs0_cfg { 149*4882a593Smuzhiyun pins = "p1_5"; 150*4882a593Smuzhiyun function = "emc"; 151*4882a593Smuzhiyun slew-rate = <1>; 152*4882a593Smuzhiyun bias-disable; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun emc_sdram_dqm0_1_cfg { 156*4882a593Smuzhiyun pins = "p6_12", "p6_10"; 157*4882a593Smuzhiyun function = "emc"; 158*4882a593Smuzhiyun slew-rate = <1>; 159*4882a593Smuzhiyun bias-disable; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun emc_sdram_ras_cas_cfg { 163*4882a593Smuzhiyun pins = "p6_5", "p6_4"; 164*4882a593Smuzhiyun function = "emc"; 165*4882a593Smuzhiyun slew-rate = <1>; 166*4882a593Smuzhiyun bias-disable; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun emc_sdram_dycs0_cfg { 170*4882a593Smuzhiyun pins = "p6_9"; 171*4882a593Smuzhiyun function = "emc"; 172*4882a593Smuzhiyun slew-rate = <1>; 173*4882a593Smuzhiyun bias-disable; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun emc_sdram_cke_cfg { 177*4882a593Smuzhiyun pins = "p6_11"; 178*4882a593Smuzhiyun function = "emc"; 179*4882a593Smuzhiyun slew-rate = <1>; 180*4882a593Smuzhiyun bias-disable; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun emc_sdram_clock_cfg { 184*4882a593Smuzhiyun pins = "clk0"; 185*4882a593Smuzhiyun function = "emc"; 186*4882a593Smuzhiyun input-enable; 187*4882a593Smuzhiyun input-schmitt-disable; 188*4882a593Smuzhiyun slew-rate = <1>; 189*4882a593Smuzhiyun bias-disable; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun enet_rmii_pins: enet-rmii-pins { 194*4882a593Smuzhiyun enet_rmii_rxd_cfg { 195*4882a593Smuzhiyun pins = "p1_15", "p0_0"; 196*4882a593Smuzhiyun function = "enet"; 197*4882a593Smuzhiyun input-enable; 198*4882a593Smuzhiyun input-schmitt-disable; 199*4882a593Smuzhiyun slew-rate = <1>; 200*4882a593Smuzhiyun bias-disable; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun enet_rmii_txd_cfg { 204*4882a593Smuzhiyun pins = "p1_18", "p1_20"; 205*4882a593Smuzhiyun function = "enet"; 206*4882a593Smuzhiyun slew-rate = <1>; 207*4882a593Smuzhiyun bias-disable; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun enet_rmii_rx_dv_cfg { 211*4882a593Smuzhiyun pins = "p1_16"; 212*4882a593Smuzhiyun function = "enet"; 213*4882a593Smuzhiyun input-enable; 214*4882a593Smuzhiyun input-schmitt-disable; 215*4882a593Smuzhiyun bias-disable; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun enet_mdio_cfg { 219*4882a593Smuzhiyun pins = "p1_17"; 220*4882a593Smuzhiyun function = "enet"; 221*4882a593Smuzhiyun input-enable; 222*4882a593Smuzhiyun input-schmitt-disable; 223*4882a593Smuzhiyun bias-disable; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun enet_mdc_cfg { 227*4882a593Smuzhiyun pins = "pc_1"; 228*4882a593Smuzhiyun function = "enet"; 229*4882a593Smuzhiyun slew-rate = <1>; 230*4882a593Smuzhiyun bias-disable; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun enet_rmii_tx_en_cfg { 234*4882a593Smuzhiyun pins = "p0_1"; 235*4882a593Smuzhiyun function = "enet"; 236*4882a593Smuzhiyun bias-disable; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun enet_ref_clk_cfg { 240*4882a593Smuzhiyun pins = "p1_19"; 241*4882a593Smuzhiyun function = "enet"; 242*4882a593Smuzhiyun slew-rate = <1>; 243*4882a593Smuzhiyun input-enable; 244*4882a593Smuzhiyun input-schmitt-disable; 245*4882a593Smuzhiyun bias-disable; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun i2c0_pins: i2c0-pins { 250*4882a593Smuzhiyun i2c0_pins_cfg { 251*4882a593Smuzhiyun pins = "i2c0_scl", "i2c0_sda"; 252*4882a593Smuzhiyun function = "i2c0"; 253*4882a593Smuzhiyun input-enable; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun i2c1_pins: i2c1-pins { 258*4882a593Smuzhiyun i2c1_pins_cfg { 259*4882a593Smuzhiyun pins = "pe_15", "pe_13"; 260*4882a593Smuzhiyun function = "i2c1"; 261*4882a593Smuzhiyun input-enable; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun lcd_pins: lcd-pins { 266*4882a593Smuzhiyun lcd_vd0_23_cfg { 267*4882a593Smuzhiyun pins = "p4_1", "p4_4", "p4_3", "p4_2", 268*4882a593Smuzhiyun "p8_7", "p8_6", "p8_5", "p8_4", 269*4882a593Smuzhiyun "p7_5", "p4_8", "p4_10", "p4_9", 270*4882a593Smuzhiyun "p8_3", "pb_6", "pb_5", "pb_4", 271*4882a593Smuzhiyun "p7_4", "p7_3", "p7_2", "p7_1", 272*4882a593Smuzhiyun "pb_3", "pb_2", "pb_1", "pb_0"; 273*4882a593Smuzhiyun function = "lcd"; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun lcd_vsync_en_dclk_lp_pwr_cfg { 277*4882a593Smuzhiyun pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; 278*4882a593Smuzhiyun function = "lcd"; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun led_pins: led-pins { 283*4882a593Smuzhiyun led_1_6_cfg { 284*4882a593Smuzhiyun pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; 285*4882a593Smuzhiyun function = "gpio"; 286*4882a593Smuzhiyun bias-pull-down; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun sdmmc_pins: sdmmc-pins { 291*4882a593Smuzhiyun sdmmc_clk_cfg { 292*4882a593Smuzhiyun pins = "pc_0"; 293*4882a593Smuzhiyun function = "sdmmc"; 294*4882a593Smuzhiyun slew-rate = <1>; 295*4882a593Smuzhiyun bias-pull-down; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun sdmmc_cmd_dat0_3_cfg { 299*4882a593Smuzhiyun pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; 300*4882a593Smuzhiyun function = "sdmmc"; 301*4882a593Smuzhiyun input-enable; 302*4882a593Smuzhiyun input-schmitt-disable; 303*4882a593Smuzhiyun slew-rate = <1>; 304*4882a593Smuzhiyun bias-disable; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun sdmmc_cd_cfg { 308*4882a593Smuzhiyun pins = "pc_8"; 309*4882a593Smuzhiyun function = "sdmmc"; 310*4882a593Smuzhiyun input-enable; 311*4882a593Smuzhiyun bias-pull-down; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun spifi_pins: spifi-pins { 316*4882a593Smuzhiyun spifi_sck_cfg { 317*4882a593Smuzhiyun pins = "p3_3"; 318*4882a593Smuzhiyun function = "spifi"; 319*4882a593Smuzhiyun input-enable; 320*4882a593Smuzhiyun input-schmitt-disable; 321*4882a593Smuzhiyun slew-rate = <1>; 322*4882a593Smuzhiyun bias-disable; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun spifi_mosi_miso_sio2_sio3_cfg { 326*4882a593Smuzhiyun pins = "p3_7", "p3_6", "p3_5", "p3_4"; 327*4882a593Smuzhiyun function = "spifi"; 328*4882a593Smuzhiyun input-enable; 329*4882a593Smuzhiyun input-schmitt-disable; 330*4882a593Smuzhiyun slew-rate = <1>; 331*4882a593Smuzhiyun bias-disable; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun spifi_cs_cfg { 335*4882a593Smuzhiyun pins = "p3_8"; 336*4882a593Smuzhiyun function = "spifi"; 337*4882a593Smuzhiyun bias-disable; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun ssp1_pins: ssp1-pins { 342*4882a593Smuzhiyun ssp1_sck_cfg { 343*4882a593Smuzhiyun pins = "pf_4"; 344*4882a593Smuzhiyun function = "ssp1"; 345*4882a593Smuzhiyun slew-rate = <1>; 346*4882a593Smuzhiyun bias-pull-down; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun ssp1_miso_cfg { 350*4882a593Smuzhiyun pins = "pf_6"; 351*4882a593Smuzhiyun function = "ssp1"; 352*4882a593Smuzhiyun input-enable; 353*4882a593Smuzhiyun input-schmitt-disable; 354*4882a593Smuzhiyun slew-rate = <1>; 355*4882a593Smuzhiyun bias-pull-down; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun ssp1_mosi_cfg { 359*4882a593Smuzhiyun pins = "pf_7"; 360*4882a593Smuzhiyun function = "ssp1"; 361*4882a593Smuzhiyun slew-rate = <1>; 362*4882a593Smuzhiyun bias-pull-down; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun ssp1_ssel_cfg { 366*4882a593Smuzhiyun pins = "pf_5"; 367*4882a593Smuzhiyun function = "gpio"; 368*4882a593Smuzhiyun bias-disable; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun uart0_pins: uart0-pins { 373*4882a593Smuzhiyun uart0_rxd_cfg { 374*4882a593Smuzhiyun pins = "pf_11"; 375*4882a593Smuzhiyun function = "uart0"; 376*4882a593Smuzhiyun input-enable; 377*4882a593Smuzhiyun input-schmitt-disable; 378*4882a593Smuzhiyun bias-disable; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun uart0_clk_dir_txd_cfg { 382*4882a593Smuzhiyun pins = "pf_8", "pf_9", "pf_10"; 383*4882a593Smuzhiyun function = "uart0"; 384*4882a593Smuzhiyun bias-pull-down; 385*4882a593Smuzhiyun }; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun uart1_pins: uart1-pins { 389*4882a593Smuzhiyun uart1_rxd_cfg { 390*4882a593Smuzhiyun pins = "pc_14"; 391*4882a593Smuzhiyun function = "uart1"; 392*4882a593Smuzhiyun bias-disable; 393*4882a593Smuzhiyun input-enable; 394*4882a593Smuzhiyun input-schmitt-disable; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun uart1_dtr_txd_cfg { 398*4882a593Smuzhiyun pins = "pc_12", "pc_13"; 399*4882a593Smuzhiyun function = "uart1"; 400*4882a593Smuzhiyun bias-pull-down; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun uart2_pins: uart2-pins { 405*4882a593Smuzhiyun uart2_rxd_cfg { 406*4882a593Smuzhiyun pins = "pa_2"; 407*4882a593Smuzhiyun function = "uart2"; 408*4882a593Smuzhiyun bias-disable; 409*4882a593Smuzhiyun input-enable; 410*4882a593Smuzhiyun input-schmitt-disable; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun uart2_txd_cfg { 414*4882a593Smuzhiyun pins = "pa_1"; 415*4882a593Smuzhiyun function = "uart2"; 416*4882a593Smuzhiyun bias-pull-down; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun uart3_pins: uart3-pins { 421*4882a593Smuzhiyun uart3_rx_cfg { 422*4882a593Smuzhiyun pins = "p2_4"; 423*4882a593Smuzhiyun function = "uart3"; 424*4882a593Smuzhiyun bias-disable; 425*4882a593Smuzhiyun input-enable; 426*4882a593Smuzhiyun input-schmitt-disable; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun uart3_tx_cfg { 430*4882a593Smuzhiyun pins = "p2_3"; 431*4882a593Smuzhiyun function = "uart3"; 432*4882a593Smuzhiyun bias-pull-down; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun usb0_pins: usb0-pins { 437*4882a593Smuzhiyun usb0_pwr_enable_cfg { 438*4882a593Smuzhiyun pins = "p6_3"; 439*4882a593Smuzhiyun function = "usb0"; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun usb0_pwr_fault_cfg { 443*4882a593Smuzhiyun pins = "p8_0"; 444*4882a593Smuzhiyun function = "usb0"; 445*4882a593Smuzhiyun bias-disable; 446*4882a593Smuzhiyun input-enable; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun}; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun&adc1 { 452*4882a593Smuzhiyun status = "okay"; 453*4882a593Smuzhiyun vref-supply = <&vcc>; 454*4882a593Smuzhiyun}; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun&can0 { 457*4882a593Smuzhiyun status = "okay"; 458*4882a593Smuzhiyun pinctrl-names = "default"; 459*4882a593Smuzhiyun pinctrl-0 = <&can0_pins>; 460*4882a593Smuzhiyun}; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun/* Pin conflict with EMC, muxed by JP5 and JP6 */ 463*4882a593Smuzhiyun&can1 { 464*4882a593Smuzhiyun status = "disabled"; 465*4882a593Smuzhiyun pinctrl-names = "default"; 466*4882a593Smuzhiyun pinctrl-0 = <&can1_pins>; 467*4882a593Smuzhiyun}; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun&emc { 470*4882a593Smuzhiyun status = "okay"; 471*4882a593Smuzhiyun pinctrl-names = "default"; 472*4882a593Smuzhiyun pinctrl-0 = <&emc_pins>; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun cs0 { 475*4882a593Smuzhiyun #address-cells = <2>; 476*4882a593Smuzhiyun #size-cells = <1>; 477*4882a593Smuzhiyun ranges; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun mpmc,cs = <0>; 480*4882a593Smuzhiyun mpmc,memory-width = <16>; 481*4882a593Smuzhiyun mpmc,byte-lane-low; 482*4882a593Smuzhiyun mpmc,write-enable-delay = <0>; 483*4882a593Smuzhiyun mpmc,output-enable-delay = <0>; 484*4882a593Smuzhiyun mpmc,read-access-delay = <70>; 485*4882a593Smuzhiyun mpmc,page-mode-read-delay = <70>; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun /* SST/Microchip SST39VF1601 */ 488*4882a593Smuzhiyun flash@0,0 { 489*4882a593Smuzhiyun compatible = "cfi-flash"; 490*4882a593Smuzhiyun reg = <0 0 0x400000>; 491*4882a593Smuzhiyun bank-width = <2>; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun}; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun&enet_tx_clk { 497*4882a593Smuzhiyun clock-frequency = <50000000>; 498*4882a593Smuzhiyun}; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun&i2c0 { 501*4882a593Smuzhiyun status = "okay"; 502*4882a593Smuzhiyun pinctrl-names = "default"; 503*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 504*4882a593Smuzhiyun clock-frequency = <400000>; 505*4882a593Smuzhiyun}; 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun&i2c1 { 508*4882a593Smuzhiyun status = "okay"; 509*4882a593Smuzhiyun pinctrl-names = "default"; 510*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 511*4882a593Smuzhiyun clock-frequency = <400000>; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun sensor@49 { 514*4882a593Smuzhiyun compatible = "lm75"; 515*4882a593Smuzhiyun reg = <0x49>; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun eeprom@50 { 519*4882a593Smuzhiyun compatible = "atmel,24c512"; 520*4882a593Smuzhiyun reg = <0x50>; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun}; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun&lcdc { 525*4882a593Smuzhiyun status = "okay"; 526*4882a593Smuzhiyun pinctrl-names = "default"; 527*4882a593Smuzhiyun pinctrl-0 = <&lcd_pins>; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun max-memory-bandwidth = <92240000>; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun port { 532*4882a593Smuzhiyun lcdc_output: endpoint { 533*4882a593Smuzhiyun remote-endpoint = <&panel_input>; 534*4882a593Smuzhiyun arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun }; 537*4882a593Smuzhiyun}; 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun&mac { 540*4882a593Smuzhiyun status = "okay"; 541*4882a593Smuzhiyun phy-mode = "rmii"; 542*4882a593Smuzhiyun pinctrl-names = "default"; 543*4882a593Smuzhiyun pinctrl-0 = <&enet_rmii_pins>; 544*4882a593Smuzhiyun phy-handle = <&phy1>; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun mdio0 { 547*4882a593Smuzhiyun #address-cells = <1>; 548*4882a593Smuzhiyun #size-cells = <0>; 549*4882a593Smuzhiyun compatible = "snps,dwmac-mdio"; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun phy1: ethernet-phy@1 { 552*4882a593Smuzhiyun reg = <1>; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun}; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun&mmcsd { 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun pinctrl-names = "default"; 560*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_pins>; 561*4882a593Smuzhiyun bus-width = <4>; 562*4882a593Smuzhiyun vmmc-supply = <&vmmc>; 563*4882a593Smuzhiyun}; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun/* Pin conflict with SSP0, the latter is routed to J17 pin header */ 566*4882a593Smuzhiyun&spifi { 567*4882a593Smuzhiyun status = "okay"; 568*4882a593Smuzhiyun pinctrl-names = "default"; 569*4882a593Smuzhiyun pinctrl-0 = <&spifi_pins>; 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun /* Atmel AT25DF321A */ 572*4882a593Smuzhiyun flash { 573*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 574*4882a593Smuzhiyun spi-max-frequency = <51000000>; 575*4882a593Smuzhiyun spi-cpol; 576*4882a593Smuzhiyun spi-cpha; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun}; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun&ssp1 { 581*4882a593Smuzhiyun status = "okay"; 582*4882a593Smuzhiyun pinctrl-names = "default"; 583*4882a593Smuzhiyun pinctrl-0 = <&ssp1_pins>; 584*4882a593Smuzhiyun num-cs = <1>; 585*4882a593Smuzhiyun cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; 586*4882a593Smuzhiyun}; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun/* Routed to J17 pin header */ 589*4882a593Smuzhiyun&uart0 { 590*4882a593Smuzhiyun status = "okay"; 591*4882a593Smuzhiyun pinctrl-names = "default"; 592*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 593*4882a593Smuzhiyun}; 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun/* RS485 */ 596*4882a593Smuzhiyun&uart1 { 597*4882a593Smuzhiyun status = "okay"; 598*4882a593Smuzhiyun pinctrl-names = "default"; 599*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 600*4882a593Smuzhiyun}; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun/* Routed to J17 pin header */ 603*4882a593Smuzhiyun&uart2 { 604*4882a593Smuzhiyun status = "okay"; 605*4882a593Smuzhiyun pinctrl-names = "default"; 606*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 607*4882a593Smuzhiyun}; 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun&uart3 { 610*4882a593Smuzhiyun status = "okay"; 611*4882a593Smuzhiyun pinctrl-names = "default"; 612*4882a593Smuzhiyun pinctrl-0 = <&uart3_pins>; 613*4882a593Smuzhiyun}; 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun&usb0 { 616*4882a593Smuzhiyun status = "okay"; 617*4882a593Smuzhiyun pinctrl-names = "default"; 618*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 619*4882a593Smuzhiyun}; 620