1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * NXP LPC4350 and LPC4330 SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This code is released using a dual license strategy: BSD/GPL 7*4882a593Smuzhiyun * You can choose the licence that better fits your requirements. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Released under the terms of 3-clause BSD License 10*4882a593Smuzhiyun * Released under the terms of GNU General Public License Version 2.0 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun compatible = "nxp,lpc4350", "nxp,lpc4330"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun cpu@0 { 19*4882a593Smuzhiyun compatible = "arm,cortex-m4"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun soc { 24*4882a593Smuzhiyun sram0: sram@10000000 { 25*4882a593Smuzhiyun compatible = "mmio-sram"; 26*4882a593Smuzhiyun reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun sram1: sram@10080000 { 30*4882a593Smuzhiyun compatible = "mmio-sram"; 31*4882a593Smuzhiyun reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun sram2: sram@20000000 { 35*4882a593Smuzhiyun compatible = "mmio-sram"; 36*4882a593Smuzhiyun reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun}; 40