xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/lpc4337-ciaa.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This code is released using a dual license strategy: BSD/GPL
7*4882a593Smuzhiyun * You can choose the licence that better fits your requirements.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Released under the terms of 3-clause BSD License
10*4882a593Smuzhiyun * Released under the terms of GNU General Public License Version 2.0
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun/dts-v1/;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun#include "lpc18xx.dtsi"
15*4882a593Smuzhiyun#include "lpc4357.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun#include "dt-bindings/gpio/gpio.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/ {
20*4882a593Smuzhiyun	model = "CIAA NXP LPC4337";
21*4882a593Smuzhiyun	compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350";
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	aliases {
24*4882a593Smuzhiyun		serial0 = &uart2;
25*4882a593Smuzhiyun		serial1 = &uart3;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	chosen {
29*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200 earlyprintk";
30*4882a593Smuzhiyun		stdout-path = &uart2;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	memory@28000000 {
34*4882a593Smuzhiyun		device_type = "memory";
35*4882a593Smuzhiyun		reg = <0x28000000 0x0800000>; /* 8 MB */
36*4882a593Smuzhiyun	};
37*4882a593Smuzhiyun};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun&pinctrl {
40*4882a593Smuzhiyun	enet_rmii_pins: enet-rmii-pins {
41*4882a593Smuzhiyun		enet_rmii_rxd_cfg {
42*4882a593Smuzhiyun			pins = "p1_15", "p0_0";
43*4882a593Smuzhiyun			function = "enet";
44*4882a593Smuzhiyun			slew-rate = <1>;
45*4882a593Smuzhiyun			bias-disable;
46*4882a593Smuzhiyun			input-enable;
47*4882a593Smuzhiyun			input-schmitt-disable;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		enet_rmii_txd_cfg {
51*4882a593Smuzhiyun			pins = "p1_18", "p1_20";
52*4882a593Smuzhiyun			function = "enet";
53*4882a593Smuzhiyun			slew-rate = <1>;
54*4882a593Smuzhiyun			bias-disable;
55*4882a593Smuzhiyun			input-enable;
56*4882a593Smuzhiyun			input-schmitt-disable;
57*4882a593Smuzhiyun		};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		enet_rmii_rx_dv_cfg {
60*4882a593Smuzhiyun			pins = "p1_16";
61*4882a593Smuzhiyun			function = "enet";
62*4882a593Smuzhiyun			bias-disable;
63*4882a593Smuzhiyun			input-enable;
64*4882a593Smuzhiyun			input-schmitt-disable;
65*4882a593Smuzhiyun		};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun		enet_rmii_tx_en_cfg {
68*4882a593Smuzhiyun			pins = "p0_1";
69*4882a593Smuzhiyun			function = "enet";
70*4882a593Smuzhiyun			bias-disable;
71*4882a593Smuzhiyun			input-enable;
72*4882a593Smuzhiyun			input-schmitt-disable;
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		enet_ref_clk_cfg {
76*4882a593Smuzhiyun			pins = "p1_19";
77*4882a593Smuzhiyun			function = "enet";
78*4882a593Smuzhiyun			slew-rate = <1>;
79*4882a593Smuzhiyun			bias-disable;
80*4882a593Smuzhiyun			input-enable;
81*4882a593Smuzhiyun			input-schmitt-disable;
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		enet_mdio_cfg {
85*4882a593Smuzhiyun			pins = "p1_17";
86*4882a593Smuzhiyun			function = "enet";
87*4882a593Smuzhiyun			bias-disable;
88*4882a593Smuzhiyun			input-enable;
89*4882a593Smuzhiyun			input-schmitt-disable;
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		enet_mdc_cfg {
93*4882a593Smuzhiyun			pins = "p7_7";
94*4882a593Smuzhiyun			function = "enet";
95*4882a593Smuzhiyun			slew-rate = <1>;
96*4882a593Smuzhiyun			bias-disable;
97*4882a593Smuzhiyun			input-enable;
98*4882a593Smuzhiyun			input-schmitt-disable;
99*4882a593Smuzhiyun		};
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	i2c0_pins: i2c0-pins {
103*4882a593Smuzhiyun		i2c0_pins_cfg {
104*4882a593Smuzhiyun			pins = "i2c0_scl", "i2c0_sda";
105*4882a593Smuzhiyun			function = "i2c0";
106*4882a593Smuzhiyun			input-enable;
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	ssp_pins: ssp-pins {
111*4882a593Smuzhiyun		ssp1_cs {
112*4882a593Smuzhiyun			pins = "p6_7";
113*4882a593Smuzhiyun			function = "gpio";
114*4882a593Smuzhiyun			bias-pull-up;
115*4882a593Smuzhiyun			bias-disable;
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun		ssp1_miso_mosi {
119*4882a593Smuzhiyun			pins = "p1_3", "p1_4";
120*4882a593Smuzhiyun			function = "ssp1";
121*4882a593Smuzhiyun			slew-rate = <1>;
122*4882a593Smuzhiyun			bias-pull-down;
123*4882a593Smuzhiyun			input-enable;
124*4882a593Smuzhiyun			input-schmitt-disable;
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun		ssp1_sck {
128*4882a593Smuzhiyun			pins = "pf_4";
129*4882a593Smuzhiyun			function = "ssp1";
130*4882a593Smuzhiyun			slew-rate = <1>;
131*4882a593Smuzhiyun			bias-disable;
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	uart2_pins: uart2-pins {
136*4882a593Smuzhiyun		uart2_rx_cfg {
137*4882a593Smuzhiyun			pins = "p7_2";
138*4882a593Smuzhiyun			function = "uart2";
139*4882a593Smuzhiyun			bias-disable;
140*4882a593Smuzhiyun			input-enable;
141*4882a593Smuzhiyun		};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		uart2_tx_cfg {
144*4882a593Smuzhiyun			pins = "p7_1";
145*4882a593Smuzhiyun			function = "uart2";
146*4882a593Smuzhiyun			bias-disable;
147*4882a593Smuzhiyun		};
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	uart3_pins: uart3-pins {
151*4882a593Smuzhiyun		uart3_rx_cfg {
152*4882a593Smuzhiyun			pins = "p2_4";
153*4882a593Smuzhiyun			function = "uart3";
154*4882a593Smuzhiyun			bias-disable;
155*4882a593Smuzhiyun			input-enable;
156*4882a593Smuzhiyun		};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun		uart3_tx_cfg {
159*4882a593Smuzhiyun			pins = "p2_3";
160*4882a593Smuzhiyun			function = "uart3";
161*4882a593Smuzhiyun			bias-disable;
162*4882a593Smuzhiyun		};
163*4882a593Smuzhiyun	};
164*4882a593Smuzhiyun};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun&enet_tx_clk {
167*4882a593Smuzhiyun	clock-frequency = <50000000>;
168*4882a593Smuzhiyun};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun&i2c0 {
171*4882a593Smuzhiyun	status = "okay";
172*4882a593Smuzhiyun	pinctrl-names = "default";
173*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
174*4882a593Smuzhiyun	clock-frequency = <400000>;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	eeprom@50 {
177*4882a593Smuzhiyun		compatible = "microchip,24c512", "atmel,24c512";
178*4882a593Smuzhiyun		reg = <0x50>;
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	eeprom@51 {
182*4882a593Smuzhiyun		compatible = "microchip,24c02", "atmel,24c02";
183*4882a593Smuzhiyun		reg = <0x51>;
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun	eeprom@54 {
187*4882a593Smuzhiyun		compatible = "microchip,24c512", "atmel,24c512";
188*4882a593Smuzhiyun		reg = <0x54>;
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&mac {
193*4882a593Smuzhiyun	status = "okay";
194*4882a593Smuzhiyun	phy-mode = "rmii";
195*4882a593Smuzhiyun	pinctrl-names = "default";
196*4882a593Smuzhiyun	pinctrl-0 = <&enet_rmii_pins>;
197*4882a593Smuzhiyun};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun&sct_pwm {
200*4882a593Smuzhiyun	status = "okay";
201*4882a593Smuzhiyun};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun&ssp1 {
204*4882a593Smuzhiyun	status = "okay";
205*4882a593Smuzhiyun	pinctrl-names = "default";
206*4882a593Smuzhiyun	pinctrl-0 = <&ssp_pins>;
207*4882a593Smuzhiyun	cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>;
208*4882a593Smuzhiyun	num-cs = <1>;
209*4882a593Smuzhiyun};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun&uart2 {
212*4882a593Smuzhiyun	status = "okay";
213*4882a593Smuzhiyun	pinctrl-names = "default";
214*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&uart3 {
218*4882a593Smuzhiyun	status = "okay";
219*4882a593Smuzhiyun	pinctrl-names = "default";
220*4882a593Smuzhiyun	pinctrl-0 = <&uart3_pins>;
221*4882a593Smuzhiyun};
222