1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/ { 6*4882a593Smuzhiyun chosen { 7*4882a593Smuzhiyun stdout-path = &uart1; 8*4882a593Smuzhiyun }; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun cpus { 11*4882a593Smuzhiyun cpu@0 { 12*4882a593Smuzhiyun cpu0-supply = <&vcc>; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun memory@80000000 { 17*4882a593Smuzhiyun device_type = "memory"; 18*4882a593Smuzhiyun reg = <0x80000000 0>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun leds { 22*4882a593Smuzhiyun compatible = "gpio-leds"; 23*4882a593Smuzhiyun user0 { 24*4882a593Smuzhiyun label = "user0"; 25*4882a593Smuzhiyun gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ 26*4882a593Smuzhiyun linux,default-trigger = "none"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* fixed 26MHz oscillator */ 31*4882a593Smuzhiyun hfclk_26m: oscillator { 32*4882a593Smuzhiyun #clock-cells = <0>; 33*4882a593Smuzhiyun compatible = "fixed-clock"; 34*4882a593Smuzhiyun clock-frequency = <26000000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun/* The Torpedo doesn't route the USB host pins */ 39*4882a593Smuzhiyun&usbhshost { 40*4882a593Smuzhiyun status = "disabled"; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&gpmc { 44*4882a593Smuzhiyun ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun nand@0,0 { 47*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 48*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 49*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 50*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 51*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 52*4882a593Smuzhiyun linux,mtd-name = "micron,mt29f4g16abbda3w"; 53*4882a593Smuzhiyun nand-bus-width = <16>; 54*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 55*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 56*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 57*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 58*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 59*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 60*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 61*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 62*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 63*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 64*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 65*4882a593Smuzhiyun gpmc,access-ns = <64>; 66*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 67*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 68*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 69*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 70*4882a593Smuzhiyun gpmc,device-width = <2>; 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <1>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&i2c1 { 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 79*4882a593Smuzhiyun clock-frequency = <2600000>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun twl: twl@48 { 82*4882a593Smuzhiyun reg = <0x48>; 83*4882a593Smuzhiyun interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 84*4882a593Smuzhiyun interrupt-parent = <&intc>; 85*4882a593Smuzhiyun clocks = <&hfclk_26m>; 86*4882a593Smuzhiyun clock-names = "fck"; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun twl_audio: audio { 89*4882a593Smuzhiyun compatible = "ti,twl4030-audio"; 90*4882a593Smuzhiyun codec { 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&i2c2 { 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 99*4882a593Smuzhiyun clock-frequency = <400000>; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&i2c3 { 103*4882a593Smuzhiyun pinctrl-names = "default"; 104*4882a593Smuzhiyun pinctrl-0 = <&i2c3_pins>; 105*4882a593Smuzhiyun clock-frequency = <400000>; 106*4882a593Smuzhiyun at24@50 { 107*4882a593Smuzhiyun compatible = "atmel,24c64"; 108*4882a593Smuzhiyun readonly; 109*4882a593Smuzhiyun reg = <0x50>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&omap3_pmx_core { 114*4882a593Smuzhiyun mcbsp2_pins: pinmux_mcbsp2_pins { 115*4882a593Smuzhiyun pinctrl-single,pins = < 116*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ 117*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ 118*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ 119*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ 120*4882a593Smuzhiyun >; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun uart2_pins: pinmux_uart2_pins { 123*4882a593Smuzhiyun pinctrl-single,pins = < 124*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ 125*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ 126*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 127*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 128*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ 129*4882a593Smuzhiyun >; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun mcspi1_pins: pinmux_mcspi1_pins { 132*4882a593Smuzhiyun pinctrl-single,pins = < 133*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ 134*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ 135*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ 136*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ 137*4882a593Smuzhiyun >; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun hsusb_otg_pins: pinmux_hsusb_otg_pins { 140*4882a593Smuzhiyun pinctrl-single,pins = < 141*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ 142*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ 143*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ 144*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ 147*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ 148*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ 149*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ 150*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ 151*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ 152*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ 153*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ 154*4882a593Smuzhiyun >; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun i2c1_pins: pinmux_i2c1_pins { 157*4882a593Smuzhiyun pinctrl-single,pins = < 158*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 159*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ 160*4882a593Smuzhiyun >; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun i2c2_pins: pinmux_i2c2_pins { 163*4882a593Smuzhiyun pinctrl-single,pins = < 164*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 165*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 166*4882a593Smuzhiyun >; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun i2c3_pins: pinmux_i2c3_pins { 169*4882a593Smuzhiyun pinctrl-single,pins = < 170*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ 171*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ 172*4882a593Smuzhiyun >; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&uart2 { 177*4882a593Smuzhiyun interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; 178*4882a593Smuzhiyun pinctrl-names = "default"; 179*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&mcspi1 { 183*4882a593Smuzhiyun pinctrl-names = "default"; 184*4882a593Smuzhiyun pinctrl-0 = <&mcspi1_pins>; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun#include "twl4030.dtsi" 188*4882a593Smuzhiyun#include "twl4030_omap3.dtsi" 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&twl { 191*4882a593Smuzhiyun twl_power: power { 192*4882a593Smuzhiyun compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; 193*4882a593Smuzhiyun ti,use_poweroff; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun}; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&twl_gpio { 198*4882a593Smuzhiyun ti,use-leds; 199*4882a593Smuzhiyun}; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun&twl_keypad { 202*4882a593Smuzhiyun status = "disabled"; 203*4882a593Smuzhiyun}; 204