xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/logicpd-som-lv.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	cpus {
7*4882a593Smuzhiyun		cpu@0 {
8*4882a593Smuzhiyun			cpu0-supply = <&vcc>;
9*4882a593Smuzhiyun		};
10*4882a593Smuzhiyun	};
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun	memory@80000000 {
13*4882a593Smuzhiyun		device_type = "memory";
14*4882a593Smuzhiyun		reg = <0x80000000 0>;
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	wl12xx_vmmc: wl12xx_vmmc {
18*4882a593Smuzhiyun		compatible = "regulator-fixed";
19*4882a593Smuzhiyun		regulator-name = "vwl1271";
20*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
21*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
22*4882a593Smuzhiyun		gpio = <&gpio1 3 0>;   /* gpio_3 */
23*4882a593Smuzhiyun		startup-delay-us = <70000>;
24*4882a593Smuzhiyun		enable-active-high;
25*4882a593Smuzhiyun		vin-supply = <&vaux3>;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	/* HS USB Host PHY on PORT 1 */
29*4882a593Smuzhiyun	hsusb2_phy: hsusb2_phy {
30*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
31*4882a593Smuzhiyun		reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
32*4882a593Smuzhiyun		#phy-cells = <0>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	/* fixed 26MHz oscillator */
36*4882a593Smuzhiyun	hfclk_26m: oscillator {
37*4882a593Smuzhiyun		#clock-cells = <0>;
38*4882a593Smuzhiyun		compatible = "fixed-clock";
39*4882a593Smuzhiyun		clock-frequency = <26000000>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun&gpmc {
44*4882a593Smuzhiyun	ranges = <0 0 0x30000000 0x1000000>;	/* CS0: 16MB for NAND */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	nand@0,0 {
47*4882a593Smuzhiyun		compatible = "ti,omap2-nand";
48*4882a593Smuzhiyun		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
49*4882a593Smuzhiyun		interrupt-parent = <&gpmc>;
50*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
51*4882a593Smuzhiyun			     <1 IRQ_TYPE_NONE>;	/* termcount */
52*4882a593Smuzhiyun		linux,mtd-name = "micron,mt29f4g16abbda3w";
53*4882a593Smuzhiyun		nand-bus-width = <16>;
54*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
55*4882a593Smuzhiyun		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
56*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
57*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
58*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
59*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
60*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
61*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
62*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
63*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
64*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
65*4882a593Smuzhiyun		gpmc,access-ns = <64>;
66*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
67*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
68*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
69*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
70*4882a593Smuzhiyun		gpmc,device-width = <2>;
71*4882a593Smuzhiyun		#address-cells = <1>;
72*4882a593Smuzhiyun		#size-cells = <1>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&i2c1 {
77*4882a593Smuzhiyun	pinctrl-names = "default";
78*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
79*4882a593Smuzhiyun	clock-frequency = <2600000>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	twl: twl@48 {
82*4882a593Smuzhiyun		reg = <0x48>;
83*4882a593Smuzhiyun		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
84*4882a593Smuzhiyun		interrupt-parent = <&intc>;
85*4882a593Smuzhiyun		clocks = <&hfclk_26m>;
86*4882a593Smuzhiyun		clock-names = "fck";
87*4882a593Smuzhiyun		twl_audio: audio {
88*4882a593Smuzhiyun			compatible = "ti,twl4030-audio";
89*4882a593Smuzhiyun			codec {
90*4882a593Smuzhiyun				ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
91*4882a593Smuzhiyun			};
92*4882a593Smuzhiyun		};
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun&i2c2 {
97*4882a593Smuzhiyun	pinctrl-names = "default";
98*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
99*4882a593Smuzhiyun	clock-frequency = <400000>;
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&i2c3 {
103*4882a593Smuzhiyun	pinctrl-names = "default";
104*4882a593Smuzhiyun	pinctrl-0 = <&i2c3_pins>;
105*4882a593Smuzhiyun	clock-frequency = <400000>;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	touchscreen: tsc2004@48 {
108*4882a593Smuzhiyun		compatible = "ti,tsc2004";
109*4882a593Smuzhiyun		reg = <0x48>;
110*4882a593Smuzhiyun		vio-supply = <&vaux1>;
111*4882a593Smuzhiyun		pinctrl-names = "default";
112*4882a593Smuzhiyun		pinctrl-0 = <&tsc2004_pins>;
113*4882a593Smuzhiyun		interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun		touchscreen-fuzz-x = <4>;
116*4882a593Smuzhiyun		touchscreen-fuzz-y = <7>;
117*4882a593Smuzhiyun		touchscreen-fuzz-pressure = <2>;
118*4882a593Smuzhiyun		touchscreen-size-x = <4096>;
119*4882a593Smuzhiyun		touchscreen-size-y = <4096>;
120*4882a593Smuzhiyun		touchscreen-max-pressure = <2048>;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		ti,x-plate-ohms = <280>;
123*4882a593Smuzhiyun		ti,esd-recovery-timeout-ms = <8000>;
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&mmc3 {
128*4882a593Smuzhiyun	interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
129*4882a593Smuzhiyun	pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
130*4882a593Smuzhiyun	pinctrl-names = "default";
131*4882a593Smuzhiyun	vmmc-supply = <&wl12xx_vmmc>;
132*4882a593Smuzhiyun	non-removable;
133*4882a593Smuzhiyun	bus-width = <4>;
134*4882a593Smuzhiyun	cap-power-off-card;
135*4882a593Smuzhiyun	#address-cells = <1>;
136*4882a593Smuzhiyun	#size-cells = <0>;
137*4882a593Smuzhiyun	wlcore: wlcore@2 {
138*4882a593Smuzhiyun		compatible = "ti,wl1273";
139*4882a593Smuzhiyun		reg = <2>;
140*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
141*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */
142*4882a593Smuzhiyun		ref-clock-frequency = <26000000>;
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&usbhshost {
147*4882a593Smuzhiyun	port2-mode = "ehci-phy";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&usbhsehci {
151*4882a593Smuzhiyun	phys = <0 &hsusb2_phy>;
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun&omap3_pmx_core {
156*4882a593Smuzhiyun	pinctrl-names = "default";
157*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_pins>;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	mmc3_pins: pinmux_mm3_pins {
160*4882a593Smuzhiyun		pinctrl-single,pins = <
161*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat4.sdmmc3_dat0 */
162*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat5.sdmmc3_dat1 */
163*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat6.sdmmc3_dat2 */
164*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat6.sdmmc3_dat3 */
165*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
166*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs2.sdmmc_clk */
167*4882a593Smuzhiyun		>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun	mcbsp2_pins: pinmux_mcbsp2_pins {
170*4882a593Smuzhiyun		pinctrl-single,pins = <
171*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
172*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
173*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
174*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
175*4882a593Smuzhiyun		>;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun	uart2_pins: pinmux_uart2_pins {
178*4882a593Smuzhiyun		pinctrl-single,pins = <
179*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)	/* uart2_cts.uart2_cts */
180*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)	/* uart2_rts .uart2_rts*/
181*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)	/* uart2_tx.uart2_tx */
182*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)	/* uart2_rx.uart2_rx */
183*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* GPIO_162,BT_EN */
184*4882a593Smuzhiyun		>;
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun	mcspi1_pins: pinmux_mcspi1_pins {
187*4882a593Smuzhiyun		pinctrl-single,pins = <
188*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
189*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
190*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
191*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
192*4882a593Smuzhiyun		>;
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	hsusb2_pins: pinmux_hsusb2_pins {
196*4882a593Smuzhiyun		pinctrl-single,pins = <
197*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
198*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
199*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
200*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
201*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
202*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
203*4882a593Smuzhiyun		>;
204*4882a593Smuzhiyun	};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun	hsusb_otg_pins: pinmux_hsusb_otg_pins {
207*4882a593Smuzhiyun		pinctrl-single,pins = <
208*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)	/* hsusb0_clk.hsusb0_clk */
209*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)	/* hsusb0_stp.hsusb0_stp */
210*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)	/* hsusb0_dir.hsusb0_dir */
211*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)	/* hsusb0_nxt.hsusb0_nxt */
212*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)	/* hsusb0_data0.hsusb0_data0 */
213*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)	/* hsusb0_data1.hsusb0_data1 */
214*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)	/* hsusb0_data2.hsusb0_data2 */
215*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)	/* hsusb0_data3.hsusb0_data3 */
216*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)	/* hsusb0_data4.hsusb0_data4 */
217*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)	/* hsusb0_data5.hsusb0_data5 */
218*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)	/* hsusb0_data6.hsusb0_data6 */
219*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)	/* hsusb0_data7.hsusb0_data7 */
220*4882a593Smuzhiyun		>;
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	i2c1_pins: pinmux_i2c1_pins {
224*4882a593Smuzhiyun		pinctrl-single,pins = <
225*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
226*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
227*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4)        /* gpmc_ncs6.gpio_57 */
228*4882a593Smuzhiyun		>;
229*4882a593Smuzhiyun	};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun	i2c2_pins: pinmux_i2c2_pins {
232*4882a593Smuzhiyun		pinctrl-single,pins = <
233*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
234*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
235*4882a593Smuzhiyun		>;
236*4882a593Smuzhiyun	};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun	i2c3_pins: pinmux_i2c3_pins {
239*4882a593Smuzhiyun		pinctrl-single,pins = <
240*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
241*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
242*4882a593Smuzhiyun		>;
243*4882a593Smuzhiyun	};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun	tsc2004_pins: pinmux_tsc2004_pins {
246*4882a593Smuzhiyun		pinctrl-single,pins = <
247*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4)	/* mcbsp4_dr.gpio_153 */
248*4882a593Smuzhiyun		>;
249*4882a593Smuzhiyun	};
250*4882a593Smuzhiyun};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun&omap3_pmx_wkup {
253*4882a593Smuzhiyun	pinctrl-names = "default";
254*4882a593Smuzhiyun	pinctrl-0 = <&hsusb2_reset_pin>;
255*4882a593Smuzhiyun	hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
256*4882a593Smuzhiyun		pinctrl-single,pins = <
257*4882a593Smuzhiyun			OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)	/* sys_boot2.gpio_4 */
258*4882a593Smuzhiyun		>;
259*4882a593Smuzhiyun	};
260*4882a593Smuzhiyun	wl127x_gpio: pinmux_wl127x_gpio_pin {
261*4882a593Smuzhiyun		pinctrl-single,pins = <
262*4882a593Smuzhiyun			OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4)		/* sys_boot0.gpio_2 */
263*4882a593Smuzhiyun			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
264*4882a593Smuzhiyun		>;
265*4882a593Smuzhiyun	};
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun&uart2 {
269*4882a593Smuzhiyun	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
270*4882a593Smuzhiyun	pinctrl-names = "default";
271*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
272*4882a593Smuzhiyun};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun&mcspi1 {
275*4882a593Smuzhiyun	pinctrl-names = "default";
276*4882a593Smuzhiyun	pinctrl-0 = <&mcspi1_pins>;
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun#include "twl4030.dtsi"
280*4882a593Smuzhiyun#include "twl4030_omap3.dtsi"
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&vaux3 {
283*4882a593Smuzhiyun	regulator-min-microvolt = <2800000>;
284*4882a593Smuzhiyun	regulator-max-microvolt = <2800000>;
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&twl {
288*4882a593Smuzhiyun	twl_power: power {
289*4882a593Smuzhiyun		compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
290*4882a593Smuzhiyun		ti,use_poweroff;
291*4882a593Smuzhiyun	};
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&twl_gpio {
295*4882a593Smuzhiyun	ti,use-leds;
296*4882a593Smuzhiyun};
297