1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Marvell OpenRD (Base|Client|Ultimate) Board Description 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Andrew Lunn <andrew@lunn.ch> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file contains the definitions that are common between the three 8*4882a593Smuzhiyun * variants of the Marvell Kirkwood Development Board. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "kirkwood.dtsi" 12*4882a593Smuzhiyun#include "kirkwood-6281.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun memory { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8"; 22*4882a593Smuzhiyun stdout-path = &uart0; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun ocp@f1000000 { 26*4882a593Smuzhiyun pinctrl: pin-controller@10000 { 27*4882a593Smuzhiyun pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; 28*4882a593Smuzhiyun pinctrl-names = "default"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun pmx_select28: pmx-select-rs232-rs485 { 31*4882a593Smuzhiyun marvell,pins = "mpp28"; 32*4882a593Smuzhiyun marvell,function = "gpio"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun pmx_sdio_cd: pmx-sdio-cd { 35*4882a593Smuzhiyun marvell,pins = "mpp29"; 36*4882a593Smuzhiyun marvell,function = "gpio"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun pmx_select34: pmx-select-uart-sd { 39*4882a593Smuzhiyun marvell,pins = "mpp34"; 40*4882a593Smuzhiyun marvell,function = "gpio"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun serial@12000 { 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun sata@80000 { 48*4882a593Smuzhiyun status = "okay"; 49*4882a593Smuzhiyun nr-ports = <2>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun mvsdio@90000 { 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun cd-gpios = <&gpio0 29 9>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun gpio@10100 { 56*4882a593Smuzhiyun p28 { 57*4882a593Smuzhiyun gpio-hog; 58*4882a593Smuzhiyun gpios = <28 GPIO_ACTIVE_HIGH>; 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * SelRS232or485 selects between RS-232 or RS-485 61*4882a593Smuzhiyun * mode for the second UART. 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * Low: RS-232 64*4882a593Smuzhiyun * High: RS-485 65*4882a593Smuzhiyun * 66*4882a593Smuzhiyun * To use the second UART, you need to change also 67*4882a593Smuzhiyun * the SelUARTorSD. 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun output-low; 70*4882a593Smuzhiyun line-name = "SelRS232or485"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun gpio@10140 { 74*4882a593Smuzhiyun p2 { 75*4882a593Smuzhiyun gpio-hog; 76*4882a593Smuzhiyun gpios = <2 GPIO_ACTIVE_HIGH>; 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * SelUARTorSD selects between the second UART 79*4882a593Smuzhiyun * (serial@12100) and SD (mvsdio@90000). 80*4882a593Smuzhiyun * 81*4882a593Smuzhiyun * Low: UART 82*4882a593Smuzhiyun * High: SD 83*4882a593Smuzhiyun * 84*4882a593Smuzhiyun * When changing this line make sure the newly 85*4882a593Smuzhiyun * selected device node is enabled and the 86*4882a593Smuzhiyun * previously selected device node is disabled. 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun output-high; /* Select SD by default */ 89*4882a593Smuzhiyun line-name = "SelUARTorSD"; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&nand { 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun pinctrl-0 = <&pmx_nand>; 98*4882a593Smuzhiyun pinctrl-names = "default"; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun partition@0 { 101*4882a593Smuzhiyun label = "u-boot"; 102*4882a593Smuzhiyun reg = <0x0000000 0x100000>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun partition@100000 { 106*4882a593Smuzhiyun label = "uImage"; 107*4882a593Smuzhiyun reg = <0x0100000 0x400000>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun partition@600000 { 111*4882a593Smuzhiyun label = "root"; 112*4882a593Smuzhiyun reg = <0x0600000 0x1FA00000>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&pciec { 117*4882a593Smuzhiyun status = "okay"; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&pcie0 { 121*4882a593Smuzhiyun status = "okay"; 122*4882a593Smuzhiyun}; 123