1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Marvell OpenRD Ultimate Board Description 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Andrew Lunn <andrew@lunn.ch> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file contains the definitions that are specific to OpenRD 8*4882a593Smuzhiyun * ultimate variant of the Marvell Kirkwood Development Board. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "kirkwood-openrd.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "OpenRD Ultimate"; 17*4882a593Smuzhiyun compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun ocp@f1000000 { 20*4882a593Smuzhiyun i2c@11000 { 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun clock-frequency = <400000>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cs42l51: cs42l51@4a { 25*4882a593Smuzhiyun compatible = "cirrus,cs42l51"; 26*4882a593Smuzhiyun reg = <0x4a>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&mdio { 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 36*4882a593Smuzhiyun reg = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 39*4882a593Smuzhiyun reg = <1>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunð0 { 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun ethernet0-port@0 { 46*4882a593Smuzhiyun phy-handle = <ðphy0>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunð1 { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun ethernet1-port@0 { 53*4882a593Smuzhiyun phy-handle = <ðphy1>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun}; 56