1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for LaCie 5Big Network v2 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Andrew Lunn <andrew@lunn.ch> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Based on netxbig_v2-setup.c, 10*4882a593Smuzhiyun * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun*/ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/dts-v1/; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include "kirkwood.dtsi" 17*4882a593Smuzhiyun#include "kirkwood-6281.dtsi" 18*4882a593Smuzhiyun#include "kirkwood-netxbig.dtsi" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/ { 21*4882a593Smuzhiyun model = "LaCie 5Big Network v2"; 22*4882a593Smuzhiyun compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun®ulators { 32*4882a593Smuzhiyun regulator@2 { 33*4882a593Smuzhiyun compatible = "regulator-fixed"; 34*4882a593Smuzhiyun reg = <2>; 35*4882a593Smuzhiyun regulator-name = "hdd1power"; 36*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 38*4882a593Smuzhiyun enable-active-high; 39*4882a593Smuzhiyun regulator-always-on; 40*4882a593Smuzhiyun regulator-boot-on; 41*4882a593Smuzhiyun gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun regulator@3 { 45*4882a593Smuzhiyun compatible = "regulator-fixed"; 46*4882a593Smuzhiyun reg = <3>; 47*4882a593Smuzhiyun regulator-name = "hdd2power"; 48*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 49*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 50*4882a593Smuzhiyun enable-active-high; 51*4882a593Smuzhiyun regulator-always-on; 52*4882a593Smuzhiyun regulator-boot-on; 53*4882a593Smuzhiyun gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun regulator@4 { 57*4882a593Smuzhiyun compatible = "regulator-fixed"; 58*4882a593Smuzhiyun reg = <4>; 59*4882a593Smuzhiyun regulator-name = "hdd3power"; 60*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 61*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 62*4882a593Smuzhiyun enable-active-high; 63*4882a593Smuzhiyun regulator-always-on; 64*4882a593Smuzhiyun regulator-boot-on; 65*4882a593Smuzhiyun gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun regulator@5 { 69*4882a593Smuzhiyun compatible = "regulator-fixed"; 70*4882a593Smuzhiyun reg = <5>; 71*4882a593Smuzhiyun regulator-name = "hdd4power"; 72*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 73*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 74*4882a593Smuzhiyun enable-active-high; 75*4882a593Smuzhiyun regulator-always-on; 76*4882a593Smuzhiyun regulator-boot-on; 77*4882a593Smuzhiyun gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun clocks { 81*4882a593Smuzhiyun g762_clk: g762-oscillator { 82*4882a593Smuzhiyun compatible = "fixed-clock"; 83*4882a593Smuzhiyun #clock-cells = <0>; 84*4882a593Smuzhiyun clock-frequency = <32768>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun netxbig-leds { 89*4882a593Smuzhiyun blue-sata2 { 90*4882a593Smuzhiyun label = "netxbig:blue:sata2"; 91*4882a593Smuzhiyun mode-addr = <5>; 92*4882a593Smuzhiyun mode-val = <NETXBIG_LED_OFF 0 93*4882a593Smuzhiyun NETXBIG_LED_ON 7 94*4882a593Smuzhiyun NETXBIG_LED_SATA 1 95*4882a593Smuzhiyun NETXBIG_LED_TIMER1 3>; 96*4882a593Smuzhiyun bright-addr = <2>; 97*4882a593Smuzhiyun max-brightness = <7>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun red-sata2 { 100*4882a593Smuzhiyun label = "netxbig:red:sata2"; 101*4882a593Smuzhiyun mode-addr = <5>; 102*4882a593Smuzhiyun mode-val = <NETXBIG_LED_OFF 0 103*4882a593Smuzhiyun NETXBIG_LED_ON 2 104*4882a593Smuzhiyun NETXBIG_LED_TIMER1 4>; 105*4882a593Smuzhiyun bright-addr = <2>; 106*4882a593Smuzhiyun max-brightness = <7>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun blue-sata3 { 109*4882a593Smuzhiyun label = "netxbig:blue:sata3"; 110*4882a593Smuzhiyun mode-addr = <6>; 111*4882a593Smuzhiyun mode-val = <NETXBIG_LED_OFF 0 112*4882a593Smuzhiyun NETXBIG_LED_ON 7 113*4882a593Smuzhiyun NETXBIG_LED_SATA 1 114*4882a593Smuzhiyun NETXBIG_LED_TIMER1 3>; 115*4882a593Smuzhiyun bright-addr = <2>; 116*4882a593Smuzhiyun max-brightness = <7>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun red-sata3 { 119*4882a593Smuzhiyun label = "netxbig:red:sata3"; 120*4882a593Smuzhiyun mode-addr = <6>; 121*4882a593Smuzhiyun mode-val = <NETXBIG_LED_OFF 0 122*4882a593Smuzhiyun NETXBIG_LED_ON 2 123*4882a593Smuzhiyun NETXBIG_LED_TIMER1 4>; 124*4882a593Smuzhiyun bright-addr = <2>; 125*4882a593Smuzhiyun max-brightness = <7>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun blue-sata4 { 128*4882a593Smuzhiyun label = "netxbig:blue:sata4"; 129*4882a593Smuzhiyun mode-addr = <7>; 130*4882a593Smuzhiyun mode-val = <NETXBIG_LED_OFF 0 131*4882a593Smuzhiyun NETXBIG_LED_ON 7 132*4882a593Smuzhiyun NETXBIG_LED_SATA 1 133*4882a593Smuzhiyun NETXBIG_LED_TIMER1 3>; 134*4882a593Smuzhiyun bright-addr = <2>; 135*4882a593Smuzhiyun max-brightness = <7>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun red-sata4 { 138*4882a593Smuzhiyun label = "netxbig:red:sata4"; 139*4882a593Smuzhiyun mode-addr = <7>; 140*4882a593Smuzhiyun mode-val = <NETXBIG_LED_OFF 0 141*4882a593Smuzhiyun NETXBIG_LED_ON 2 142*4882a593Smuzhiyun NETXBIG_LED_TIMER1 4>; 143*4882a593Smuzhiyun bright-addr = <2>; 144*4882a593Smuzhiyun max-brightness = <7>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&mdio { 150*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 151*4882a593Smuzhiyun reg = <0>; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyunð1 { 156*4882a593Smuzhiyun status = "okay"; 157*4882a593Smuzhiyun ethernet1-port@0 { 158*4882a593Smuzhiyun phy-handle = <ðphy1>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&i2c0 { 164*4882a593Smuzhiyun g762@3e { 165*4882a593Smuzhiyun compatible = "gmt,g762"; 166*4882a593Smuzhiyun reg = <0x3e>; 167*4882a593Smuzhiyun clocks = <&g762_clk>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun}; 170