1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for LaCie 2Big NAS 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Seagate 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Simon Guinot <simon.guinot@sequanux.org> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun*/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "kirkwood-netxbig.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "LaCie 2Big NAS"; 17*4882a593Smuzhiyun compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun chosen { 25*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8"; 26*4882a593Smuzhiyun stdout-path = &uart0; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun ocp@f1000000 { 30*4882a593Smuzhiyun rtc@10300 { 31*4882a593Smuzhiyun /* The on-chip RTC is not powered (no supercap). */ 32*4882a593Smuzhiyun status = "disabled"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun spi@10600 { 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * A NAND flash is used instead of an SPI flash for 37*4882a593Smuzhiyun * the other netxbig-compatible boards. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun status = "disabled"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun fan { 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * An I2C fan controller (GMT G762) is used but alarm is 46*4882a593Smuzhiyun * wired to a separate GPIO. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun compatible = "gpio-fan"; 49*4882a593Smuzhiyun alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun regulators: regulators { 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun compatible = "simple-bus"; 55*4882a593Smuzhiyun #address-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <0>; 57*4882a593Smuzhiyun pinctrl-names = "default"; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun regulator@2 { 60*4882a593Smuzhiyun compatible = "regulator-fixed"; 61*4882a593Smuzhiyun reg = <2>; 62*4882a593Smuzhiyun regulator-name = "hdd1power"; 63*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 64*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 65*4882a593Smuzhiyun enable-active-high; 66*4882a593Smuzhiyun regulator-always-on; 67*4882a593Smuzhiyun regulator-boot-on; 68*4882a593Smuzhiyun gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun clocks { 71*4882a593Smuzhiyun g762_clk: g762-oscillator { 72*4882a593Smuzhiyun compatible = "fixed-clock"; 73*4882a593Smuzhiyun #clock-cells = <0>; 74*4882a593Smuzhiyun clock-frequency = <32768>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&mdio { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 84*4882a593Smuzhiyun reg = <0>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&i2c0 { 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * An external I2C RTC (Dallas DS1337S+) is used. This allows 93*4882a593Smuzhiyun * to power-up the board on an RTC alarm. The external RTC can 94*4882a593Smuzhiyun * be kept powered, even when the SoC is off. 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun rtc@68 { 97*4882a593Smuzhiyun compatible = "dallas,ds1307"; 98*4882a593Smuzhiyun reg = <0x68>; 99*4882a593Smuzhiyun interrupts = <43>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun g762@3e { 102*4882a593Smuzhiyun compatible = "gmt,g762"; 103*4882a593Smuzhiyun reg = <0x3e>; 104*4882a593Smuzhiyun clocks = <&g762_clk>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&nand { 109*4882a593Smuzhiyun chip-delay = <50>; 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun partition@0 { 113*4882a593Smuzhiyun label = "U-Boot"; 114*4882a593Smuzhiyun reg = <0x0 0x100000>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun partition@100000 { 118*4882a593Smuzhiyun label = "uImage"; 119*4882a593Smuzhiyun reg = <0x100000 0x1000000>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun partition@1100000 { 123*4882a593Smuzhiyun label = "root"; 124*4882a593Smuzhiyun reg = <0x1100000 0x8000000>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun partition@9100000 { 128*4882a593Smuzhiyun label = "unused"; 129*4882a593Smuzhiyun reg = <0x9100000 0x6f00000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&pciec { 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&pcie0 { 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun}; 140