1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Marvell DB-{88F6281,88F6282}-BP Development Board Setup 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Saeed Bishara <saeed@marvell.com> 6*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file contains the definitions that are common between the 6281 9*4882a593Smuzhiyun * and 6282 variants of the Marvell Kirkwood Development Board. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "kirkwood.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun memory { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; /* 512 MB */ 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8 earlyprintk"; 22*4882a593Smuzhiyun stdout-path = &uart0; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun ocp@f1000000 { 26*4882a593Smuzhiyun pin-controller@10000 { 27*4882a593Smuzhiyun pmx_sdio_gpios: pmx-sdio-gpios { 28*4882a593Smuzhiyun marvell,pins = "mpp37", "mpp38"; 29*4882a593Smuzhiyun marvell,function = "gpio"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun serial@12000 { 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun sata@80000 { 38*4882a593Smuzhiyun nr-ports = <2>; 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun ehci@50000 { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun mvsdio@90000 { 47*4882a593Smuzhiyun pinctrl-0 = <&pmx_sdio_gpios>; 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 50*4882a593Smuzhiyun cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&nand { 57*4882a593Smuzhiyun chip-delay = <25>; 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun partition@0 { 61*4882a593Smuzhiyun label = "uboot"; 62*4882a593Smuzhiyun reg = <0x0 0x100000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun partition@100000 { 66*4882a593Smuzhiyun label = "uImage"; 67*4882a593Smuzhiyun reg = <0x100000 0x400000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun partition@500000 { 71*4882a593Smuzhiyun label = "root"; 72*4882a593Smuzhiyun reg = <0x500000 0x1fb00000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&mdio { 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun ethphy0: ethernet-phy@8 { 80*4882a593Smuzhiyun reg = <8>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunð0 { 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun ethernet0-port@0 { 87*4882a593Smuzhiyun phy-handle = <ðphy0>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90