1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Keystone 2 Kepler/Hawking EVM device tree 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "keystone.dtsi" 10*4882a593Smuzhiyun#include "keystone-k2hk.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; 14*4882a593Smuzhiyun model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reserved-memory { 17*4882a593Smuzhiyun #address-cells = <2>; 18*4882a593Smuzhiyun #size-cells = <2>; 19*4882a593Smuzhiyun ranges; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun dsp_common_memory: dsp-common-memory@81f800000 { 22*4882a593Smuzhiyun compatible = "shared-dma-pool"; 23*4882a593Smuzhiyun reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 24*4882a593Smuzhiyun reusable; 25*4882a593Smuzhiyun status = "okay"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun leds { 30*4882a593Smuzhiyun compatible = "gpio-leds"; 31*4882a593Smuzhiyun debug1_1 { 32*4882a593Smuzhiyun label = "keystone:green:debug1"; 33*4882a593Smuzhiyun gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun debug1_2 { 37*4882a593Smuzhiyun label = "keystone:red:debug1"; 38*4882a593Smuzhiyun gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun debug2 { 42*4882a593Smuzhiyun label = "keystone:blue:debug2"; 43*4882a593Smuzhiyun gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun debug3 { 47*4882a593Smuzhiyun label = "keystone:blue:debug3"; 48*4882a593Smuzhiyun gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&soc0 { 54*4882a593Smuzhiyun clocks { 55*4882a593Smuzhiyun refclksys: refclksys { 56*4882a593Smuzhiyun #clock-cells = <0>; 57*4882a593Smuzhiyun compatible = "fixed-clock"; 58*4882a593Smuzhiyun clock-frequency = <122880000>; 59*4882a593Smuzhiyun clock-output-names = "refclk-sys"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun refclkpass: refclkpass { 63*4882a593Smuzhiyun #clock-cells = <0>; 64*4882a593Smuzhiyun compatible = "fixed-clock"; 65*4882a593Smuzhiyun clock-frequency = <122880000>; 66*4882a593Smuzhiyun clock-output-names = "refclk-pass"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun refclkarm: refclkarm { 70*4882a593Smuzhiyun #clock-cells = <0>; 71*4882a593Smuzhiyun compatible = "fixed-clock"; 72*4882a593Smuzhiyun clock-frequency = <125000000>; 73*4882a593Smuzhiyun clock-output-names = "refclk-arm"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun refclkddr3a: refclkddr3a { 77*4882a593Smuzhiyun #clock-cells = <0>; 78*4882a593Smuzhiyun compatible = "fixed-clock"; 79*4882a593Smuzhiyun clock-frequency = <100000000>; 80*4882a593Smuzhiyun clock-output-names = "refclk-ddr3a"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun refclkddr3b: refclkddr3b { 84*4882a593Smuzhiyun #clock-cells = <0>; 85*4882a593Smuzhiyun compatible = "fixed-clock"; 86*4882a593Smuzhiyun clock-frequency = <100000000>; 87*4882a593Smuzhiyun clock-output-names = "refclk-ddr3b"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&usb_phy { 93*4882a593Smuzhiyun status = "okay"; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun&keystone_usb0 { 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&usb0 { 101*4882a593Smuzhiyun dr_mode = "host"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&aemif { 105*4882a593Smuzhiyun cs0 { 106*4882a593Smuzhiyun #address-cells = <2>; 107*4882a593Smuzhiyun #size-cells = <1>; 108*4882a593Smuzhiyun clock-ranges; 109*4882a593Smuzhiyun ranges; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun ti,cs-chipselect = <0>; 112*4882a593Smuzhiyun /* all timings in nanoseconds */ 113*4882a593Smuzhiyun ti,cs-min-turnaround-ns = <12>; 114*4882a593Smuzhiyun ti,cs-read-hold-ns = <6>; 115*4882a593Smuzhiyun ti,cs-read-strobe-ns = <23>; 116*4882a593Smuzhiyun ti,cs-read-setup-ns = <9>; 117*4882a593Smuzhiyun ti,cs-write-hold-ns = <8>; 118*4882a593Smuzhiyun ti,cs-write-strobe-ns = <23>; 119*4882a593Smuzhiyun ti,cs-write-setup-ns = <8>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun nand@0,0 { 122*4882a593Smuzhiyun compatible = "ti,keystone-nand","ti,davinci-nand"; 123*4882a593Smuzhiyun #address-cells = <1>; 124*4882a593Smuzhiyun #size-cells = <1>; 125*4882a593Smuzhiyun reg = <0 0 0x4000000 126*4882a593Smuzhiyun 1 0 0x0000100>; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun ti,davinci-chipselect = <0>; 129*4882a593Smuzhiyun ti,davinci-mask-ale = <0x2000>; 130*4882a593Smuzhiyun ti,davinci-mask-cle = <0x4000>; 131*4882a593Smuzhiyun ti,davinci-mask-chipsel = <0>; 132*4882a593Smuzhiyun nand-ecc-mode = "hw"; 133*4882a593Smuzhiyun ti,davinci-ecc-bits = <4>; 134*4882a593Smuzhiyun nand-on-flash-bbt; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun partition@0 { 137*4882a593Smuzhiyun label = "u-boot"; 138*4882a593Smuzhiyun reg = <0x0 0x100000>; 139*4882a593Smuzhiyun read-only; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun partition@100000 { 143*4882a593Smuzhiyun label = "params"; 144*4882a593Smuzhiyun reg = <0x100000 0x80000>; 145*4882a593Smuzhiyun read-only; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun partition@180000 { 149*4882a593Smuzhiyun label = "ubifs"; 150*4882a593Smuzhiyun reg = <0x180000 0x1fe80000>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&i2c0 { 157*4882a593Smuzhiyun dtt@50 { 158*4882a593Smuzhiyun compatible = "atmel,24c1024"; 159*4882a593Smuzhiyun reg = <0x50>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&spi0 { 164*4882a593Smuzhiyun nor_flash: n25q128a11@0 { 165*4882a593Smuzhiyun #address-cells = <1>; 166*4882a593Smuzhiyun #size-cells = <1>; 167*4882a593Smuzhiyun compatible = "Micron,n25q128a11"; 168*4882a593Smuzhiyun spi-max-frequency = <54000000>; 169*4882a593Smuzhiyun m25p,fast-read; 170*4882a593Smuzhiyun reg = <0>; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun partition@0 { 173*4882a593Smuzhiyun label = "u-boot-spl"; 174*4882a593Smuzhiyun reg = <0x0 0x80000>; 175*4882a593Smuzhiyun read-only; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun partition@1 { 179*4882a593Smuzhiyun label = "misc"; 180*4882a593Smuzhiyun reg = <0x80000 0xf80000>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&mdio { 186*4882a593Smuzhiyun status = "ok"; 187*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 188*4882a593Smuzhiyun compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; 189*4882a593Smuzhiyun reg = <0>; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 193*4882a593Smuzhiyun compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; 194*4882a593Smuzhiyun reg = <1>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&dsp0 { 199*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&dsp1 { 204*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 205*4882a593Smuzhiyun status = "okay"; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&dsp2 { 209*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&dsp3 { 214*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 215*4882a593Smuzhiyun status = "okay"; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&dsp4 { 219*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 220*4882a593Smuzhiyun status = "okay"; 221*4882a593Smuzhiyun}; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun&dsp5 { 224*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 225*4882a593Smuzhiyun status = "okay"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&dsp6 { 229*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&dsp7 { 234*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 235*4882a593Smuzhiyun status = "okay"; 236*4882a593Smuzhiyun}; 237