1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Keystone 2 Edison SoC specific device tree 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunclocks { 9*4882a593Smuzhiyun mainpllclk: mainpllclk@2310110 { 10*4882a593Smuzhiyun #clock-cells = <0>; 11*4882a593Smuzhiyun compatible = "ti,keystone,main-pll-clock"; 12*4882a593Smuzhiyun clocks = <&refclksys>; 13*4882a593Smuzhiyun reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 14*4882a593Smuzhiyun reg-names = "control", "multiplier", "post-divider"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun papllclk: papllclk@2620358 { 18*4882a593Smuzhiyun #clock-cells = <0>; 19*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 20*4882a593Smuzhiyun clocks = <&refclkpass>; 21*4882a593Smuzhiyun clock-output-names = "papllclk"; 22*4882a593Smuzhiyun reg = <0x02620358 4>; 23*4882a593Smuzhiyun reg-names = "control"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun ddr3apllclk: ddr3apllclk@2620360 { 27*4882a593Smuzhiyun #clock-cells = <0>; 28*4882a593Smuzhiyun compatible = "ti,keystone,pll-clock"; 29*4882a593Smuzhiyun clocks = <&refclkddr3a>; 30*4882a593Smuzhiyun clock-output-names = "ddr-3a-pll-clk"; 31*4882a593Smuzhiyun reg = <0x02620360 4>; 32*4882a593Smuzhiyun reg-names = "control"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clkusb1: clkusb1@2350004 { 36*4882a593Smuzhiyun #clock-cells = <0>; 37*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 38*4882a593Smuzhiyun clocks = <&chipclk16>; 39*4882a593Smuzhiyun clock-output-names = "usb1"; 40*4882a593Smuzhiyun reg = <0x02350004 0xb00>, <0x02350000 0x400>; 41*4882a593Smuzhiyun reg-names = "control", "domain"; 42*4882a593Smuzhiyun domain-id = <0>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun clkhyperlink0: clkhyperlink0@2350030 { 46*4882a593Smuzhiyun #clock-cells = <0>; 47*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 48*4882a593Smuzhiyun clocks = <&chipclk12>; 49*4882a593Smuzhiyun clock-output-names = "hyperlink-0"; 50*4882a593Smuzhiyun reg = <0x02350030 0xb00>, <0x02350014 0x400>; 51*4882a593Smuzhiyun reg-names = "control", "domain"; 52*4882a593Smuzhiyun domain-id = <5>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun clkpcie1: clkpcie1@235006c { 56*4882a593Smuzhiyun #clock-cells = <0>; 57*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 58*4882a593Smuzhiyun clocks = <&chipclk12>; 59*4882a593Smuzhiyun clock-output-names = "pcie1"; 60*4882a593Smuzhiyun reg = <0x0235006c 0xb00>, <0x02350048 0x400>; 61*4882a593Smuzhiyun reg-names = "control", "domain"; 62*4882a593Smuzhiyun domain-id = <18>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun clkxge: clkxge@23500c8 { 66*4882a593Smuzhiyun #clock-cells = <0>; 67*4882a593Smuzhiyun compatible = "ti,keystone,psc-clock"; 68*4882a593Smuzhiyun clocks = <&chipclk13>; 69*4882a593Smuzhiyun clock-output-names = "xge"; 70*4882a593Smuzhiyun reg = <0x023500c8 0xb00>, <0x02350074 0x400>; 71*4882a593Smuzhiyun reg-names = "control", "domain"; 72*4882a593Smuzhiyun domain-id = <29>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * Below are set of fixed, input clocks definitions, 77*4882a593Smuzhiyun * for which real frequencies have to be defined in board files. 78*4882a593Smuzhiyun * Those clocks can be used as reference clocks for some HW modules 79*4882a593Smuzhiyun * (as cpts, for example) by configuring corresponding clock muxes. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun tsipclka: tsipclka { 82*4882a593Smuzhiyun #clock-cells = <0>; 83*4882a593Smuzhiyun compatible = "fixed-clock"; 84*4882a593Smuzhiyun clock-frequency = <0>; 85*4882a593Smuzhiyun clock-output-names = "tsipclka"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun tsipclkb: tsipclkb { 89*4882a593Smuzhiyun #clock-cells = <0>; 90*4882a593Smuzhiyun compatible = "fixed-clock"; 91*4882a593Smuzhiyun clock-frequency = <0>; 92*4882a593Smuzhiyun clock-output-names = "tsipclkb"; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95