1*4882a593Smuzhiyun// SPDX-License-Identifier: ISC 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Intel XScale Network Processors 4*4882a593Smuzhiyun * in the IXP 4xx series. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun soc { 11*4882a593Smuzhiyun #address-cells = <1>; 12*4882a593Smuzhiyun #size-cells = <1>; 13*4882a593Smuzhiyun ranges; 14*4882a593Smuzhiyun compatible = "simple-bus"; 15*4882a593Smuzhiyun interrupt-parent = <&intcon>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun qmgr: queue-manager@60000000 { 18*4882a593Smuzhiyun compatible = "intel,ixp4xx-ahb-queue-manager"; 19*4882a593Smuzhiyun reg = <0x60000000 0x4000>; 20*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun uart0: serial@c8000000 { 24*4882a593Smuzhiyun compatible = "intel,xscale-uart"; 25*4882a593Smuzhiyun reg = <0xc8000000 0x1000>; 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * The reg-offset and reg-shift is a side effect 28*4882a593Smuzhiyun * of running the platform in big endian mode. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun reg-offset = <3>; 31*4882a593Smuzhiyun reg-shift = <2>; 32*4882a593Smuzhiyun interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; 33*4882a593Smuzhiyun clock-frequency = <14745600>; 34*4882a593Smuzhiyun no-loopback-test; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun gpio0: gpio@c8004000 { 38*4882a593Smuzhiyun compatible = "intel,ixp4xx-gpio"; 39*4882a593Smuzhiyun reg = <0xc8004000 0x1000>; 40*4882a593Smuzhiyun gpio-controller; 41*4882a593Smuzhiyun #gpio-cells = <2>; 42*4882a593Smuzhiyun interrupt-controller; 43*4882a593Smuzhiyun #interrupt-cells = <2>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun intcon: interrupt-controller@c8003000 { 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * Note: no compatible string. The subvariant of the 49*4882a593Smuzhiyun * chip needs to define what version it is. The 50*4882a593Smuzhiyun * location of the interrupt controller is fixed in 51*4882a593Smuzhiyun * memory across all variants. 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun reg = <0xc8003000 0x100>; 54*4882a593Smuzhiyun interrupt-controller; 55*4882a593Smuzhiyun #interrupt-cells = <2>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun timer@c8005000 { 59*4882a593Smuzhiyun compatible = "intel,ixp4xx-timer"; 60*4882a593Smuzhiyun reg = <0xc8005000 0x100>; 61*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun npe@c8006000 { 65*4882a593Smuzhiyun compatible = "intel,ixp4xx-network-processing-engine"; 66*4882a593Smuzhiyun reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70