1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DTS_IMX7ULP_PINFUNC_H 8*4882a593Smuzhiyun #define __DTS_IMX7ULP_PINFUNC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * The pin function ID is a tuple of 12*4882a593Smuzhiyun * <mux_conf_reg input_reg mux_mode input_val> 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 16*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 17*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 18*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 19*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 20*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 21*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 22*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 23*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 24*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 25*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 26*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 27*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 28*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 29*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 30*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 31*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 32*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 33*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 34*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 35*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 36*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 37*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 38*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 39*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 40*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 41*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 42*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 43*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 44*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 45*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 46*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 47*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 48*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 49*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 50*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 51*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 52*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 53*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 54*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 55*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 56*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 57*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 58*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 59*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 60*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 61*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 62*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 63*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 64*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 65*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 66*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 67*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 68*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 69*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 70*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 71*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 72*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 73*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 74*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 75*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 76*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 77*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 78*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 79*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 80*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 81*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 82*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 83*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 84*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 85*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 86*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 87*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 88*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 89*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 90*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 91*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 92*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 93*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 94*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 95*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 96*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 97*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 98*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 99*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 100*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 101*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 102*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 103*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 104*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 105*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 106*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 107*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 108*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 109*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 110*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 111*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 112*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 113*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 114*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 115*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 116*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 117*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 118*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 119*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 120*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 121*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 122*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 123*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 124*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 125*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 126*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 127*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 128*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 129*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 130*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 131*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 132*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 133*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 134*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 135*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 136*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 137*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 138*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 139*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 140*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 141*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 142*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 143*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 144*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 145*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 146*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 147*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 148*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 149*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 150*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 151*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 152*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 153*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 154*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 155*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 156*4882a593Smuzhiyun #define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 157*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 158*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 159*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 160*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 161*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 162*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 163*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 164*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 165*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 166*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 167*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 168*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 169*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 170*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 171*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 172*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 173*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 174*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 175*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 176*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 177*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 178*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 179*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 180*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 181*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 182*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 183*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 184*4882a593Smuzhiyun #define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 185*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 186*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 187*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 188*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 189*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 190*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 191*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 192*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 193*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 194*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 195*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 196*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 197*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 198*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 199*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 200*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 201*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 202*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 203*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 204*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 205*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 206*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 207*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 208*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 209*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 210*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 211*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 212*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 213*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 214*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 215*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 216*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 217*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 218*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 219*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 220*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 221*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 222*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 223*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 224*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 225*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 226*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 227*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 228*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 229*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 230*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 231*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 232*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 233*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 234*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 235*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 236*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 237*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 238*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 239*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 240*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 241*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 242*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 243*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 244*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 245*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 246*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 247*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 248*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 249*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 250*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 251*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 252*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 253*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 254*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 255*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 256*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 257*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 258*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 259*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 260*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 261*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 262*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 263*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 264*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 265*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 266*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 267*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 268*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 269*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 270*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 271*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 272*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 273*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 274*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 275*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 276*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 277*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 278*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 279*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 280*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 281*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 282*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 283*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 284*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 285*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 286*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 287*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 288*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 289*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 290*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 291*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 292*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 293*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 294*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 295*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 296*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 297*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 298*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 299*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 300*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 301*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 302*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 303*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 304*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 305*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 306*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 307*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 308*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 309*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 310*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 311*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 312*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 313*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 314*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 315*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 316*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 317*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 318*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 319*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 320*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 321*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 322*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 323*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 324*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 325*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 326*4882a593Smuzhiyun #define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 327*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 328*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 329*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 330*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 331*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 332*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 333*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 334*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 335*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 336*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 337*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 338*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 339*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 340*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 341*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 342*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 343*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 344*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 345*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 346*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 347*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 348*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 349*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 350*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 351*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 352*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 353*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 354*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 355*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 356*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 357*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 358*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 359*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 360*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 361*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 362*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 363*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 364*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 365*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 366*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 367*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 368*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 369*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 370*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 371*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 372*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 373*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 374*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 375*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 376*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 377*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 378*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 379*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 380*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 381*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 382*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 383*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 384*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 385*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 386*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 387*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 388*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 389*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 390*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 391*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 392*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 393*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 394*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 395*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 396*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 397*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 398*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 399*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 400*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 401*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 402*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 403*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 404*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 405*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 406*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 407*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 408*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 409*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 410*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 411*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 412*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 413*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 414*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 415*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 416*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 417*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 418*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 419*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 420*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 421*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 422*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 423*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 424*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 425*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 426*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 427*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 428*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 429*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 430*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 431*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 432*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 433*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 434*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 435*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 436*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 437*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 438*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 439*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 440*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 441*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 442*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 443*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 444*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 445*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 446*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 447*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 448*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 449*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 450*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 451*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 452*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 453*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 454*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 455*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 456*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 457*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 458*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 459*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 460*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 461*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 462*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 463*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 464*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 465*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 466*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 467*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 468*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 469*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 470*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 471*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 472*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 473*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 474*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 475*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 476*4882a593Smuzhiyun #define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun #endif /* __DTS_IMX7ULP_PINFUNC_H */ 479