xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx7-mba7.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR X11
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Include file for TQ Systems MBa7 carrier board.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 TQ Systems GmbH
6*4882a593Smuzhiyun * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7*4882a593Smuzhiyun * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Note: This file does not include nodes for all peripheral devices.
10*4882a593Smuzhiyun * As device driver coverage increases additional nodes can be added.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
14*4882a593Smuzhiyun#include <dt-bindings/net/ti-dp83867.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	beeper {
18*4882a593Smuzhiyun		compatible = "gpio-beeper";
19*4882a593Smuzhiyun		gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	chosen {
23*4882a593Smuzhiyun		stdout-path = &uart6;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	gpio_buttons: gpio-keys {
27*4882a593Smuzhiyun		compatible = "gpio-keys";
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		button-0 {
30*4882a593Smuzhiyun			/* #SWITCH_A */
31*4882a593Smuzhiyun			label = "S11";
32*4882a593Smuzhiyun			linux,code = <KEY_1>;
33*4882a593Smuzhiyun			gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		button-1 {
37*4882a593Smuzhiyun			/* #SWITCH_B */
38*4882a593Smuzhiyun			label = "S12";
39*4882a593Smuzhiyun			linux,code = <KEY_2>;
40*4882a593Smuzhiyun			gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		button-2 {
44*4882a593Smuzhiyun			/* #SWITCH_C */
45*4882a593Smuzhiyun			label = "S13";
46*4882a593Smuzhiyun			linux,code = <KEY_3>;
47*4882a593Smuzhiyun			gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	gpio-leds {
52*4882a593Smuzhiyun		compatible = "gpio-leds";
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		led1 {
55*4882a593Smuzhiyun			label = "led1";
56*4882a593Smuzhiyun			gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
57*4882a593Smuzhiyun			linux,default-trigger = "default-on";
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		led2 {
61*4882a593Smuzhiyun			label = "led2";
62*4882a593Smuzhiyun			gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
63*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	reg_sd1_vmmc: regulator-sd1-vmmc {
68*4882a593Smuzhiyun		compatible = "regulator-fixed";
69*4882a593Smuzhiyun		regulator-name = "VCC3V3_SD1";
70*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
71*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
72*4882a593Smuzhiyun		regulator-always-on;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	reg_fec1_pwdn: regulator-fec1-pwdn {
76*4882a593Smuzhiyun		compatible = "regulator-fixed";
77*4882a593Smuzhiyun		regulator-name = "PWDN_FEC1";
78*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
79*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
80*4882a593Smuzhiyun		regulator-always-on;
81*4882a593Smuzhiyun		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
82*4882a593Smuzhiyun		enable-active-high;
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	reg_fec2_pwdn: regulator-fec2-pwdn {
86*4882a593Smuzhiyun		compatible = "regulator-fixed";
87*4882a593Smuzhiyun		regulator-name = "PWDN_FEC2";
88*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
89*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
90*4882a593Smuzhiyun		regulator-always-on;
91*4882a593Smuzhiyun		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
92*4882a593Smuzhiyun		enable-active-high;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
96*4882a593Smuzhiyun		compatible = "regulator-fixed";
97*4882a593Smuzhiyun		regulator-name = "VBUS_USBOTG1";
98*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
99*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
100*4882a593Smuzhiyun		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
101*4882a593Smuzhiyun		enable-active-high;
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
105*4882a593Smuzhiyun		compatible = "regulator-fixed";
106*4882a593Smuzhiyun		regulator-name = "VBUS_USBOTG2";
107*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
108*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
109*4882a593Smuzhiyun		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
110*4882a593Smuzhiyun		enable-active-high;
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	reg_mpcie_1v5: regulator-mpcie-1v5 {
114*4882a593Smuzhiyun		compatible = "regulator-fixed";
115*4882a593Smuzhiyun		regulator-name = "VCC1V5_MPCIE";
116*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
117*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
118*4882a593Smuzhiyun		gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
119*4882a593Smuzhiyun		enable-active-high;
120*4882a593Smuzhiyun		regulator-always-on;
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun	reg_mpcie_3v3: regulator-mpcie-3v3 {
124*4882a593Smuzhiyun		compatible = "regulator-fixed";
125*4882a593Smuzhiyun		regulator-name = "VCC3V3_MPCIE";
126*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
127*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
128*4882a593Smuzhiyun		gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
129*4882a593Smuzhiyun		enable-active-high;
130*4882a593Smuzhiyun		regulator-always-on;
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	reg_mba_12v0: regulator-mba-12v0 {
134*4882a593Smuzhiyun		compatible = "regulator-fixed";
135*4882a593Smuzhiyun		regulator-name = "VCC12V0_MBA7";
136*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
137*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
138*4882a593Smuzhiyun		gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
139*4882a593Smuzhiyun		enable-active-high;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	reg_lvds_transmitter: regulator-lvds-transmitter {
143*4882a593Smuzhiyun		compatible = "regulator-fixed";
144*4882a593Smuzhiyun		regulator-name = "#SHTDN_LVDS";
145*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
146*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
147*4882a593Smuzhiyun		gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
148*4882a593Smuzhiyun		enable-active-high;
149*4882a593Smuzhiyun	};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun	reg_vref_1v8: regulator-vref-1v8 {
152*4882a593Smuzhiyun		compatible = "regulator-fixed";
153*4882a593Smuzhiyun		regulator-name = "VCC1V8_REF";
154*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
155*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
156*4882a593Smuzhiyun		regulator-always-on;
157*4882a593Smuzhiyun		vin-supply = <&sw2_reg>;
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	reg_audio_3v3: regulator-audio-3v3 {
161*4882a593Smuzhiyun		compatible = "regulator-fixed";
162*4882a593Smuzhiyun		regulator-name = "VCC3V3_AUDIO";
163*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
164*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
165*4882a593Smuzhiyun		regulator-always-on;
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&adc1 {
170*4882a593Smuzhiyun	vref-supply = <&reg_vref_1v8>;
171*4882a593Smuzhiyun	status = "okay";
172*4882a593Smuzhiyun};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun&adc2 {
175*4882a593Smuzhiyun	vref-supply = <&reg_vref_1v8>;
176*4882a593Smuzhiyun	status = "okay";
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&ecspi1 {
180*4882a593Smuzhiyun	pinctrl-names = "default";
181*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
182*4882a593Smuzhiyun	num-chipselects = <3>;
183*4882a593Smuzhiyun	cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
184*4882a593Smuzhiyun		   <&gpio4 2 GPIO_ACTIVE_LOW>;
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&ecspi2 {
189*4882a593Smuzhiyun	pinctrl-names = "default";
190*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi2>;
191*4882a593Smuzhiyun	num-chipselects = <1>;
192*4882a593Smuzhiyun	status = "okay";
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&fec1 {
196*4882a593Smuzhiyun	pinctrl-names = "default";
197*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet1>;
198*4882a593Smuzhiyun	phy-mode = "rgmii-id";
199*4882a593Smuzhiyun	phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
200*4882a593Smuzhiyun	phy-reset-duration = <1>;
201*4882a593Smuzhiyun	phy-reset-delay = <1>;
202*4882a593Smuzhiyun	phy-supply = <&reg_fec1_pwdn>;
203*4882a593Smuzhiyun	phy-handle = <&ethphy1_0>;
204*4882a593Smuzhiyun	fsl,magic-packet;
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	mdio {
208*4882a593Smuzhiyun		#address-cells = <1>;
209*4882a593Smuzhiyun		#size-cells = <0>;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun		ethphy1_0: ethernet-phy@0 {
212*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
213*4882a593Smuzhiyun			reg = <0>;
214*4882a593Smuzhiyun			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
215*4882a593Smuzhiyun			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
216*4882a593Smuzhiyun			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
217*4882a593Smuzhiyun			/* LED1: Link/Activity, LED2: Error */
218*4882a593Smuzhiyun			ti,led-function = <0x0db0>;
219*4882a593Smuzhiyun			/* Active low, LED1 and LED2 driven by phy */
220*4882a593Smuzhiyun			ti,led-ctrl = <0x1001>;
221*4882a593Smuzhiyun		};
222*4882a593Smuzhiyun	};
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&flexcan1 {
226*4882a593Smuzhiyun	pinctrl-names = "default";
227*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
228*4882a593Smuzhiyun	status = "okay";
229*4882a593Smuzhiyun};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun&flexcan2 {
232*4882a593Smuzhiyun	pinctrl-names = "default";
233*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
234*4882a593Smuzhiyun	status = "okay";
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun&i2c1 {
238*4882a593Smuzhiyun	lm75: temperature-sensor@49 {
239*4882a593Smuzhiyun		compatible = "national,lm75";
240*4882a593Smuzhiyun		reg = <0x49>;
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&i2c2 {
245*4882a593Smuzhiyun	clock-frequency = <100000>;
246*4882a593Smuzhiyun	pinctrl-names = "default";
247*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
248*4882a593Smuzhiyun	status = "okay";
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun	tlv320aic32x4: audio-codec@18 {
251*4882a593Smuzhiyun		compatible = "ti,tlv320aic32x4";
252*4882a593Smuzhiyun		reg = <0x18>;
253*4882a593Smuzhiyun		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
254*4882a593Smuzhiyun		clock-names = "mclk";
255*4882a593Smuzhiyun		ldoin-supply = <&reg_audio_3v3>;
256*4882a593Smuzhiyun		iov-supply = <&reg_audio_3v3>;
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun	pca9555: gpio-expander@20 {
260*4882a593Smuzhiyun		compatible = "nxp,pca9555";
261*4882a593Smuzhiyun		reg = <0x20>;
262*4882a593Smuzhiyun		pinctrl-names = "default";
263*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pca9555>;
264*4882a593Smuzhiyun		gpio-controller;
265*4882a593Smuzhiyun		#gpio-cells = <2>;
266*4882a593Smuzhiyun		interrupt-parent = <&gpio7>;
267*4882a593Smuzhiyun		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
268*4882a593Smuzhiyun		interrupt-controller;
269*4882a593Smuzhiyun		#interrupt-cells = <2>;
270*4882a593Smuzhiyun	};
271*4882a593Smuzhiyun};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun&i2c3 {
274*4882a593Smuzhiyun	clock-frequency = <100000>;
275*4882a593Smuzhiyun	pinctrl-names = "default";
276*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
277*4882a593Smuzhiyun	status = "okay";
278*4882a593Smuzhiyun};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun&iomuxc {
281*4882a593Smuzhiyun	pinctrl-names = "default";
282*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog_mba7_1>;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
285*4882a593Smuzhiyun		fsl,pins = <
286*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO		0x7c
287*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI		0x74
288*4882a593Smuzhiyun			MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK		0x74
289*4882a593Smuzhiyun			MX7D_PAD_UART1_RX_DATA__GPIO4_IO0		0x74
290*4882a593Smuzhiyun			MX7D_PAD_UART1_TX_DATA__GPIO4_IO1		0x74
291*4882a593Smuzhiyun			MX7D_PAD_UART2_RX_DATA__GPIO4_IO2		0x74
292*4882a593Smuzhiyun		>;
293*4882a593Smuzhiyun	};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun	pinctrl_ecspi2: ecspi2grp {
296*4882a593Smuzhiyun		fsl,pins = <
297*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO		0x7c
298*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI		0x74
299*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK		0x74
300*4882a593Smuzhiyun			MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0			0x74
301*4882a593Smuzhiyun		>;
302*4882a593Smuzhiyun	};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	pinctrl_enet1: enet1grp {
305*4882a593Smuzhiyun		fsl,pins = <
306*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x02
307*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x00
308*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x71
309*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x71
310*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x71
311*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x71
312*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x71
313*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71
314*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x79
315*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x79
316*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x79
317*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x79
318*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x79
319*4882a593Smuzhiyun			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79
320*4882a593Smuzhiyun			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
321*4882a593Smuzhiyun			MX7D_PAD_ENET1_COL__GPIO7_IO15		0x40000070
322*4882a593Smuzhiyun			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
323*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO09__GPIO1_IO9		0x40000078
324*4882a593Smuzhiyun		>;
325*4882a593Smuzhiyun	};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
328*4882a593Smuzhiyun		fsl,pins = <
329*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x5a
330*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x52
331*4882a593Smuzhiyun		>;
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
335*4882a593Smuzhiyun		fsl,pins = <
336*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x5a
337*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x52
338*4882a593Smuzhiyun		>;
339*4882a593Smuzhiyun	};
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun	pinctrl_hog_mba7_1: hogmba71grp {
342*4882a593Smuzhiyun		fsl,pins = <
343*4882a593Smuzhiyun			/* Limitation: WDOG2_B / WDOG2_RESET not usable */
344*4882a593Smuzhiyun			MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13	0x4000007c
345*4882a593Smuzhiyun			MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x40000074
346*4882a593Smuzhiyun			/* #BOOT_EN */
347*4882a593Smuzhiyun			MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x40000010
348*4882a593Smuzhiyun		>;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
352*4882a593Smuzhiyun		fsl,pins = <
353*4882a593Smuzhiyun			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x40000078
354*4882a593Smuzhiyun			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x40000078
355*4882a593Smuzhiyun		>;
356*4882a593Smuzhiyun	};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
359*4882a593Smuzhiyun		fsl,pins = <
360*4882a593Smuzhiyun			MX7D_PAD_I2C3_SCL__I2C3_SCL		0x40000078
361*4882a593Smuzhiyun			MX7D_PAD_I2C3_SDA__I2C3_SDA		0x40000078
362*4882a593Smuzhiyun		>;
363*4882a593Smuzhiyun	};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun	pinctrl_pca9555: pca95550grp {
367*4882a593Smuzhiyun		fsl,pins = <
368*4882a593Smuzhiyun			MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12	0x78
369*4882a593Smuzhiyun		>;
370*4882a593Smuzhiyun	};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
373*4882a593Smuzhiyun		fsl,pins = <
374*4882a593Smuzhiyun			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x7e
375*4882a593Smuzhiyun			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x76
376*4882a593Smuzhiyun			MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x76
377*4882a593Smuzhiyun			MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x7e
378*4882a593Smuzhiyun		>;
379*4882a593Smuzhiyun	};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun	pinctrl_uart4: uart4grp {
382*4882a593Smuzhiyun		fsl,pins = <
383*4882a593Smuzhiyun			MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX	0x7e
384*4882a593Smuzhiyun			MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX	0x76
385*4882a593Smuzhiyun			MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS	0x76
386*4882a593Smuzhiyun			MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS	0x7e
387*4882a593Smuzhiyun		>;
388*4882a593Smuzhiyun	};
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun	pinctrl_uart5: uart5grp {
391*4882a593Smuzhiyun		fsl,pins = <
392*4882a593Smuzhiyun			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x7e
393*4882a593Smuzhiyun			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x76
394*4882a593Smuzhiyun		>;
395*4882a593Smuzhiyun	};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun	pinctrl_uart6: uart6grp {
398*4882a593Smuzhiyun		fsl,pins = <
399*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x7d
400*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x75
401*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x75
402*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x7d
403*4882a593Smuzhiyun		>;
404*4882a593Smuzhiyun	};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun	pinctrl_uart7: uart7grp {
407*4882a593Smuzhiyun		fsl,pins = <
408*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA12__UART7_DCE_RX	0x7e
409*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA13__UART7_DCE_TX	0x76
410*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS	0x76
411*4882a593Smuzhiyun			/* Limitation: RTS is not connected */
412*4882a593Smuzhiyun			MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS	0x7e
413*4882a593Smuzhiyun		>;
414*4882a593Smuzhiyun	};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun	pinctrl_usdhc1_gpio: usdhc1grp_gpio {
417*4882a593Smuzhiyun		fsl,pins = <
418*4882a593Smuzhiyun			/* WP */
419*4882a593Smuzhiyun			MX7D_PAD_SD1_WP__GPIO5_IO1		0x7c
420*4882a593Smuzhiyun			/* CD */
421*4882a593Smuzhiyun			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x7c
422*4882a593Smuzhiyun			/* VSELECT */
423*4882a593Smuzhiyun			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59
424*4882a593Smuzhiyun		>;
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
428*4882a593Smuzhiyun		fsl,pins = <
429*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x5e
430*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x57
431*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5e
432*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5e
433*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5e
434*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5e
435*4882a593Smuzhiyun		>;
436*4882a593Smuzhiyun	};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
439*4882a593Smuzhiyun		fsl,pins = <
440*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
441*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x57
442*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
443*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
444*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
445*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
446*4882a593Smuzhiyun		>;
447*4882a593Smuzhiyun	};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
450*4882a593Smuzhiyun		fsl,pins = <
451*4882a593Smuzhiyun			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
452*4882a593Smuzhiyun			MX7D_PAD_SD1_CLK__SD1_CLK		0x57
453*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
454*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
455*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
456*4882a593Smuzhiyun			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
457*4882a593Smuzhiyun		>;
458*4882a593Smuzhiyun	};
459*4882a593Smuzhiyun};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun&iomuxc_lpsr {
462*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
463*4882a593Smuzhiyun		fsl,pins = <
464*4882a593Smuzhiyun			/* LCD_CONTRAST */
465*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x50
466*4882a593Smuzhiyun		>;
467*4882a593Smuzhiyun	};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun	pinctrl_usbotg1: usbotg1grp {
470*4882a593Smuzhiyun		fsl,pins = <
471*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x5c
472*4882a593Smuzhiyun			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x59
473*4882a593Smuzhiyun		>;
474*4882a593Smuzhiyun	};
475*4882a593Smuzhiyun};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun&pwm1 {
478*4882a593Smuzhiyun	pinctrl-names = "default";
479*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
480*4882a593Smuzhiyun	status = "okay";
481*4882a593Smuzhiyun};
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun&uart3 {
484*4882a593Smuzhiyun	pinctrl-names = "default";
485*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
486*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
487*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
488*4882a593Smuzhiyun	status = "okay";
489*4882a593Smuzhiyun};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun&uart4 {
492*4882a593Smuzhiyun	pinctrl-names = "default";
493*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
494*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
495*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
496*4882a593Smuzhiyun	status = "okay";
497*4882a593Smuzhiyun};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun&uart5 {
500*4882a593Smuzhiyun	pinctrl-names = "default";
501*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart5>;
502*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
503*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
504*4882a593Smuzhiyun	status = "okay";
505*4882a593Smuzhiyun};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun&uart6 {
508*4882a593Smuzhiyun	pinctrl-names = "default";
509*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart6>;
510*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
511*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
512*4882a593Smuzhiyun	status = "okay";
513*4882a593Smuzhiyun};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun&uart7 {
516*4882a593Smuzhiyun	pinctrl-names = "default";
517*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart7>;
518*4882a593Smuzhiyun	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
519*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
520*4882a593Smuzhiyun	uart-has-rtscts;
521*4882a593Smuzhiyun	status = "okay";
522*4882a593Smuzhiyun};
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun&usbh {
525*4882a593Smuzhiyun	status = "okay";
526*4882a593Smuzhiyun};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun&usbotg1 {
529*4882a593Smuzhiyun	pinctrl-names = "default";
530*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg1>;
531*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg1_vbus>;
532*4882a593Smuzhiyun	srp-disable;
533*4882a593Smuzhiyun	hnp-disable;
534*4882a593Smuzhiyun	adp-disable;
535*4882a593Smuzhiyun	dr_mode = "host";
536*4882a593Smuzhiyun	status = "okay";
537*4882a593Smuzhiyun};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun&usdhc1 {
540*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
541*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
542*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
543*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
544*4882a593Smuzhiyun	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
545*4882a593Smuzhiyun	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
546*4882a593Smuzhiyun	vmmc-supply = <&reg_sd1_vmmc>;
547*4882a593Smuzhiyun	bus-width = <4>;
548*4882a593Smuzhiyun	no-1-8-v;
549*4882a593Smuzhiyun	status = "okay";
550*4882a593Smuzhiyun};
551