1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR MIT 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2019 Armadeus Systems <support@armadeus.com> 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun#include "imx6ull-opos6ul.dtsi" 7*4882a593Smuzhiyun#include "imx6ul-imx6ull-opos6uldev.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board"; 11*4882a593Smuzhiyun compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull"; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&iomuxc_snvs { 15*4882a593Smuzhiyun pinctrl-names = "default"; 16*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_tamper_gpios>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun pinctrl_tamper_gpios: tampergpiosgrp { 19*4882a593Smuzhiyun fsl,pins = < 20*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 21*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 22*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 23*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 24*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 25*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 26*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 27*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 28*4882a593Smuzhiyun >; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun pinctrl_usbotg2_vbus: usbotg2vbusgrp { 32*4882a593Smuzhiyun fsl,pins = < 33*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 34*4882a593Smuzhiyun >; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun pinctrl_w1: w1grp { 38*4882a593Smuzhiyun fsl,pins = < 39*4882a593Smuzhiyun MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 40*4882a593Smuzhiyun >; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43