1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2015 Technexion Ltd. 4*4882a593Smuzhiyun// 5*4882a593Smuzhiyun// Author: Wig Cheng <wig.cheng@technexion.com> 6*4882a593Smuzhiyun// Richard Hu <richard.hu@technexion.com> 7*4882a593Smuzhiyun// Tapani Utriainen <tapani@technexion.com> 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "imx6ul-pico.dtsi" 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; 13*4882a593Smuzhiyun compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun leds { 16*4882a593Smuzhiyun compatible = "gpio-leds"; 17*4882a593Smuzhiyun pinctrl-names = "default"; 18*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun led { 21*4882a593Smuzhiyun label = "gpio-led"; 22*4882a593Smuzhiyun gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun sound { 27*4882a593Smuzhiyun compatible = "fsl,imx-audio-sgtl5000"; 28*4882a593Smuzhiyun model = "imx6ul-sgtl5000"; 29*4882a593Smuzhiyun audio-cpu = <&sai1>; 30*4882a593Smuzhiyun audio-codec = <&sgtl5000>; 31*4882a593Smuzhiyun audio-routing = 32*4882a593Smuzhiyun "LINE_IN", "Line In Jack", 33*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 34*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 35*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun sys_mclk: clock-sys-mclk { 39*4882a593Smuzhiyun compatible = "fixed-clock"; 40*4882a593Smuzhiyun #clock-cells = <0>; 41*4882a593Smuzhiyun clock-frequency = <24576000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&i2c2 { 46*4882a593Smuzhiyun clock-frequency = <100000>; 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun sgtl5000: codec@a { 52*4882a593Smuzhiyun reg = <0x0a>; 53*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 54*4882a593Smuzhiyun clocks = <&sys_mclk>; 55*4882a593Smuzhiyun VDDA-supply = <®_2p5v>; 56*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&i2c3 { 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun polytouch: touchscreen@38 { 64*4882a593Smuzhiyun compatible = "edt,edt-ft5x06"; 65*4882a593Smuzhiyun reg = <0x38>; 66*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 67*4882a593Smuzhiyun interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 68*4882a593Smuzhiyun reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 69*4882a593Smuzhiyun touchscreen-size-x = <800>; 70*4882a593Smuzhiyun touchscreen-size-y = <480>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun adc081c: adc@50 { 74*4882a593Smuzhiyun compatible = "ti,adc081c"; 75*4882a593Smuzhiyun reg = <0x50>; 76*4882a593Smuzhiyun vref-supply = <®_3p3v>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&iomuxc { 81*4882a593Smuzhiyun pinctrl-names = "default"; 82*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun pinctrl_hog: hoggrp { 85*4882a593Smuzhiyun fsl,pins = < 86*4882a593Smuzhiyun MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 87*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 88*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 89*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 90*4882a593Smuzhiyun MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 91*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 92*4882a593Smuzhiyun >; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 96*4882a593Smuzhiyun fsl,pins = < 97*4882a593Smuzhiyun MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 98*4882a593Smuzhiyun >; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101