1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2017 exceet electronics GmbH 4*4882a593Smuzhiyun * Copyright (C) 2018 Kontron Electronics GmbH 5*4882a593Smuzhiyun * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun chosen { 12*4882a593Smuzhiyun stdout-path = &uart4; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun}; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun&ecspi2 { 17*4882a593Smuzhiyun cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi2>; 20*4882a593Smuzhiyun status = "okay"; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun flash@0 { 23*4882a593Smuzhiyun compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; 24*4882a593Smuzhiyun spi-max-frequency = <50000000>; 25*4882a593Smuzhiyun reg = <0>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&fec1 { 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; 32*4882a593Smuzhiyun phy-mode = "rmii"; 33*4882a593Smuzhiyun phy-handle = <ðphy1>; 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun mdio { 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <0>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 41*4882a593Smuzhiyun reg = <1>; 42*4882a593Smuzhiyun micrel,led-mode = <0>; 43*4882a593Smuzhiyun clocks = <&clks IMX6UL_CLK_ENET_REF>; 44*4882a593Smuzhiyun clock-names = "rmii-ref"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&fec2 { 50*4882a593Smuzhiyun phy-mode = "rmii"; 51*4882a593Smuzhiyun status = "disabled"; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&qspi { 55*4882a593Smuzhiyun pinctrl-names = "default"; 56*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_qspi>; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&wdog1 { 61*4882a593Smuzhiyun pinctrl-names = "default"; 62*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 63*4882a593Smuzhiyun fsl,ext-reset-output; 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&iomuxc { 68*4882a593Smuzhiyun pinctrl-names = "default"; 69*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_reset_out>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pinctrl_ecspi2: ecspi2grp { 72*4882a593Smuzhiyun fsl,pins = < 73*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 74*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 75*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 76*4882a593Smuzhiyun MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 77*4882a593Smuzhiyun >; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pinctrl_enet1: enet1grp { 81*4882a593Smuzhiyun fsl,pins = < 82*4882a593Smuzhiyun MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 83*4882a593Smuzhiyun MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 84*4882a593Smuzhiyun MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 85*4882a593Smuzhiyun MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 86*4882a593Smuzhiyun MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 87*4882a593Smuzhiyun MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 88*4882a593Smuzhiyun MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 89*4882a593Smuzhiyun MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 90*4882a593Smuzhiyun >; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun pinctrl_enet1_mdio: enet1mdiogrp { 94*4882a593Smuzhiyun fsl,pins = < 95*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 96*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 97*4882a593Smuzhiyun >; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pinctrl_qspi: qspigrp { 101*4882a593Smuzhiyun fsl,pins = < 102*4882a593Smuzhiyun MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 103*4882a593Smuzhiyun MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 104*4882a593Smuzhiyun MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 105*4882a593Smuzhiyun MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 106*4882a593Smuzhiyun MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 107*4882a593Smuzhiyun MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 108*4882a593Smuzhiyun >; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun pinctrl_reset_out: rstoutgrp { 112*4882a593Smuzhiyun fsl,pins = < 113*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 114*4882a593Smuzhiyun >; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 118*4882a593Smuzhiyun fsl,pins = < 119*4882a593Smuzhiyun MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 120*4882a593Smuzhiyun >; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun}; 123