xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2019 Armadeus Systems <support@armadeus.com>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	memory@80000000 {
7*4882a593Smuzhiyun		device_type = "memory";
8*4882a593Smuzhiyun		reg = <0x80000000 0>; /* will be filled by U-Boot */
9*4882a593Smuzhiyun	};
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	reg_3v3: regulator-3v3 {
12*4882a593Smuzhiyun		compatible = "regulator-fixed";
13*4882a593Smuzhiyun		regulator-name = "3V3";
14*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
15*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	usdhc3_pwrseq: usdhc3-pwrseq {
19*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
20*4882a593Smuzhiyun		reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun&fec1 {
25*4882a593Smuzhiyun	pinctrl-names = "default";
26*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet1>;
27*4882a593Smuzhiyun	phy-mode = "rmii";
28*4882a593Smuzhiyun	phy-reset-duration = <1>;
29*4882a593Smuzhiyun	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
30*4882a593Smuzhiyun	phy-handle = <&ethphy1>;
31*4882a593Smuzhiyun	phy-supply = <&reg_3v3>;
32*4882a593Smuzhiyun	status = "okay";
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	mdio: mdio {
35*4882a593Smuzhiyun		#address-cells = <1>;
36*4882a593Smuzhiyun		#size-cells = <0>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		ethphy1: ethernet-phy@1 {
39*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
40*4882a593Smuzhiyun			reg = <1>;
41*4882a593Smuzhiyun			interrupt-parent = <&gpio4>;
42*4882a593Smuzhiyun			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
43*4882a593Smuzhiyun			status = "okay";
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun/* Bluetooth */
49*4882a593Smuzhiyun&uart8 {
50*4882a593Smuzhiyun	pinctrl-names = "default";
51*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart8>;
52*4882a593Smuzhiyun	uart-has-rtscts;
53*4882a593Smuzhiyun	status = "okay";
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun/* eMMC */
57*4882a593Smuzhiyun&usdhc1 {
58*4882a593Smuzhiyun	pinctrl-names = "default";
59*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
60*4882a593Smuzhiyun	bus-width = <8>;
61*4882a593Smuzhiyun	no-1-8-v;
62*4882a593Smuzhiyun	non-removable;
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun/* WiFi */
67*4882a593Smuzhiyun&usdhc2 {
68*4882a593Smuzhiyun	pinctrl-names = "default";
69*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
70*4882a593Smuzhiyun	bus-width = <4>;
71*4882a593Smuzhiyun	no-1-8-v;
72*4882a593Smuzhiyun	non-removable;
73*4882a593Smuzhiyun	mmc-pwrseq = <&usdhc3_pwrseq>;
74*4882a593Smuzhiyun	status = "okay";
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	#address-cells = <1>;
77*4882a593Smuzhiyun	#size-cells = <0>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	brcmf: wifi@1 {
80*4882a593Smuzhiyun		compatible = "brcm,bcm4329-fmac";
81*4882a593Smuzhiyun		reg = <1>;
82*4882a593Smuzhiyun		interrupt-parent = <&gpio2>;
83*4882a593Smuzhiyun		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
84*4882a593Smuzhiyun		interrupt-names = "host-wake";
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&iomuxc {
89*4882a593Smuzhiyun	pinctrl_enet1: enet1grp {
90*4882a593Smuzhiyun		fsl,pins = <
91*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
92*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
93*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
94*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
95*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
96*4882a593Smuzhiyun			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
97*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
98*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
99*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
100*4882a593Smuzhiyun			/* INT# */
101*4882a593Smuzhiyun			MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
102*4882a593Smuzhiyun			/* RST# */
103*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
104*4882a593Smuzhiyun			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
105*4882a593Smuzhiyun		>;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	pinctrl_uart8: uart8grp {
109*4882a593Smuzhiyun		fsl,pins = <
110*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
111*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
112*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
113*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
114*4882a593Smuzhiyun			/* BT_REG_ON */
115*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
116*4882a593Smuzhiyun		>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
120*4882a593Smuzhiyun		fsl,pins = <
121*4882a593Smuzhiyun			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
122*4882a593Smuzhiyun			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
123*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
124*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
125*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
126*4882a593Smuzhiyun			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
127*4882a593Smuzhiyun			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
128*4882a593Smuzhiyun			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
129*4882a593Smuzhiyun			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
130*4882a593Smuzhiyun			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
131*4882a593Smuzhiyun		>;
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
135*4882a593Smuzhiyun		fsl,pins = <
136*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
137*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
138*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
139*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
140*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
141*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
142*4882a593Smuzhiyun			/* WL_REG_ON */
143*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
144*4882a593Smuzhiyun			/* WL_IRQ */
145*4882a593Smuzhiyun			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
146*4882a593Smuzhiyun		>;
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun};
149