1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Digi International's ConnectCore 6UL System-On-Module device tree source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2018 Digi International, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun memory@80000000 { 11*4882a593Smuzhiyun device_type = "memory"; 12*4882a593Smuzhiyun reg = <0x80000000 0>; /* will be filled by U-Boot */ 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun reserved-memory { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <1>; 18*4882a593Smuzhiyun ranges; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun linux,cma { 21*4882a593Smuzhiyun compatible = "shared-dma-pool"; 22*4882a593Smuzhiyun reusable; 23*4882a593Smuzhiyun size = <0x4000000>; 24*4882a593Smuzhiyun linux,cma-default; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&adc1 { 30*4882a593Smuzhiyun vref-supply = <&vdda_adc_3v3>; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&gpmi { 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&i2c1 { 40*4882a593Smuzhiyun clock-frequency = <100000>; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pfuze3000: pmic@8 { 46*4882a593Smuzhiyun compatible = "fsl,pfuze3000"; 47*4882a593Smuzhiyun reg = <0x08>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun regulators { 50*4882a593Smuzhiyun int_3v3: sw1a { 51*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 52*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 53*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 54*4882a593Smuzhiyun regulator-boot-on; 55*4882a593Smuzhiyun regulator-always-on; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun regulator-state-mem { 58*4882a593Smuzhiyun regulator-off-in-suspend; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun vdd_arm_soc_in: sw1b { 63*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 64*4882a593Smuzhiyun regulator-max-microvolt = <1475000>; 65*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 66*4882a593Smuzhiyun regulator-boot-on; 67*4882a593Smuzhiyun regulator-always-on; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun regulator-state-mem { 70*4882a593Smuzhiyun regulator-on-in-suspend; 71*4882a593Smuzhiyun regulator-suspend-microvolt = <925000>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun ext_3v3: sw2 { 76*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 77*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 78*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 79*4882a593Smuzhiyun regulator-always-on; 80*4882a593Smuzhiyun regulator-boot-on; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun regulator-state-mem { 83*4882a593Smuzhiyun regulator-off-in-suspend; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun vcc_ddr3: sw3 { 88*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 89*4882a593Smuzhiyun regulator-max-microvolt = <1650000>; 90*4882a593Smuzhiyun regulator-always-on; 91*4882a593Smuzhiyun regulator-boot-on; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun regulator-state-mem { 94*4882a593Smuzhiyun regulator-on-in-suspend; 95*4882a593Smuzhiyun regulator-suspend-microvolt = <1300000>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun swbst_reg: swbst { 100*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 101*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun vdd_snvs_3v3: vsnvs { 105*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 106*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 107*4882a593Smuzhiyun regulator-boot-on; 108*4882a593Smuzhiyun regulator-always-on; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun vrefddr: vrefddr { 112*4882a593Smuzhiyun regulator-boot-on; 113*4882a593Smuzhiyun regulator-always-on; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun vdda_adc_3v3: vldo1 { 117*4882a593Smuzhiyun compatible = "regulator-fixed"; 118*4882a593Smuzhiyun regulator-name = "vref-adc-3v3"; 119*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 120*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 121*4882a593Smuzhiyun regulator-always-on; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun regulator-state-mem { 124*4882a593Smuzhiyun regulator-off-in-suspend; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun ldo2_ext: vldo2 { 129*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 130*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun vdda_wlan: vccsd { 134*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 135*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 136*4882a593Smuzhiyun regulator-always-on; 137*4882a593Smuzhiyun regulator-boot-on; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun regulator-state-mem { 140*4882a593Smuzhiyun regulator-off-in-suspend; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun vdd_high_in: v33 { 145*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 146*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 147*4882a593Smuzhiyun regulator-boot-on; 148*4882a593Smuzhiyun regulator-always-on; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun ldo3_int: vldo3 { 152*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 153*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun ldo4_ext: vldo4 { 157*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 158*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun vcoin_chg: vcoin { 162*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 163*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun/* UART1 (Bluetooth) */ 170*4882a593Smuzhiyun&uart1 { 171*4882a593Smuzhiyun pinctrl-names = "default"; 172*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 173*4882a593Smuzhiyun uart-has-rtscts; 174*4882a593Smuzhiyun status = "okay"; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun/* USDHC1 (Wireless) */ 178*4882a593Smuzhiyun&usdhc1 { 179*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 180*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>; 181*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>; 182*4882a593Smuzhiyun non-removable; 183*4882a593Smuzhiyun no-1-8-v; 184*4882a593Smuzhiyun bus-width = <4>; 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&iomuxc { 189*4882a593Smuzhiyun pinctrl_gpmi_nand: gpmigrp { 190*4882a593Smuzhiyun fsl,pins = < 191*4882a593Smuzhiyun MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 192*4882a593Smuzhiyun MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 193*4882a593Smuzhiyun MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 194*4882a593Smuzhiyun MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 195*4882a593Smuzhiyun MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 196*4882a593Smuzhiyun MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 197*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 198*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 199*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 200*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 201*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 202*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 203*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 204*4882a593Smuzhiyun MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 205*4882a593Smuzhiyun MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 206*4882a593Smuzhiyun >; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 210*4882a593Smuzhiyun fsl,pins = < 211*4882a593Smuzhiyun MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 212*4882a593Smuzhiyun MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 213*4882a593Smuzhiyun >; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 217*4882a593Smuzhiyun fsl,pins = < 218*4882a593Smuzhiyun MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 219*4882a593Smuzhiyun MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 220*4882a593Smuzhiyun MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1 221*4882a593Smuzhiyun MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1 222*4882a593Smuzhiyun >; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun pinctrl_usdhc1: usdhc1grp { 226*4882a593Smuzhiyun fsl,pins = < 227*4882a593Smuzhiyun MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 228*4882a593Smuzhiyun MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051 229*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 230*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 231*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 232*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 233*4882a593Smuzhiyun >; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun pinctrl_usdhc1_sleep: usdhc1grp-sleep { 237*4882a593Smuzhiyun fsl,pins = < 238*4882a593Smuzhiyun MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000 239*4882a593Smuzhiyun MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000 240*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000 241*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000 242*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000 243*4882a593Smuzhiyun MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000 244*4882a593Smuzhiyun >; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun pinctrl_wifibt_ctrl: wifibt-ctrl-grp { 248*4882a593Smuzhiyun fsl,pins = < 249*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0 250*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0 251*4882a593Smuzhiyun >; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep { 255*4882a593Smuzhiyun fsl,pins = < 256*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000 257*4882a593Smuzhiyun MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000 258*4882a593Smuzhiyun >; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun®_arm { 263*4882a593Smuzhiyun vin-supply = <&vdd_arm_soc_in>; 264*4882a593Smuzhiyun regulator-allow-bypass; 265*4882a593Smuzhiyun}; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun®_soc { 268*4882a593Smuzhiyun vin-supply = <&vdd_arm_soc_in>; 269*4882a593Smuzhiyun regulator-allow-bypass; 270*4882a593Smuzhiyun}; 271