1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "imx6sx.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Softing VIN|ING 2000"; 14*4882a593Smuzhiyun compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = &uart1; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory@80000000 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x80000000 0x40000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg_usb_otg1_vbus: regulator-usb_otg1_vbus { 26*4882a593Smuzhiyun compatible = "regulator-fixed"; 27*4882a593Smuzhiyun regulator-name = "usb_otg1_vbus"; 28*4882a593Smuzhiyun pinctrl-names = "default"; 29*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_otg1>; 30*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 31*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 32*4882a593Smuzhiyun gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 33*4882a593Smuzhiyun enable-active-high; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun reg_peri_3v3: regulator-peri_3v3 { 37*4882a593Smuzhiyun compatible = "regulator-fixed"; 38*4882a593Smuzhiyun regulator-name = "peri_3v3"; 39*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 40*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun pwmleds { 44*4882a593Smuzhiyun compatible = "pwm-leds"; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun red { 47*4882a593Smuzhiyun label = "red"; 48*4882a593Smuzhiyun max-brightness = <255>; 49*4882a593Smuzhiyun pwms = <&pwm6 0 50000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun green { 53*4882a593Smuzhiyun label = "green"; 54*4882a593Smuzhiyun max-brightness = <255>; 55*4882a593Smuzhiyun pwms = <&pwm2 0 50000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun blue { 59*4882a593Smuzhiyun label = "blue"; 60*4882a593Smuzhiyun max-brightness = <255>; 61*4882a593Smuzhiyun pwms = <&pwm1 0 50000>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&adc1 { 67*4882a593Smuzhiyun vref-supply = <®_peri_3v3>; 68*4882a593Smuzhiyun status = "okay"; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&cpu0 { 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * This board has a shared rail of reg_arm and reg_soc (supplied by 74*4882a593Smuzhiyun * sw1a_reg) which is modeled below, but still this module behaves 75*4882a593Smuzhiyun * unstable without higher voltages. Hence, set higher voltages here. 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun operating-points = < 78*4882a593Smuzhiyun /* kHz uV */ 79*4882a593Smuzhiyun 996000 1250000 80*4882a593Smuzhiyun 792000 1175000 81*4882a593Smuzhiyun 396000 1175000 82*4882a593Smuzhiyun 198000 1175000 83*4882a593Smuzhiyun >; 84*4882a593Smuzhiyun fsl,soc-operating-points = < 85*4882a593Smuzhiyun /* ARM kHz SOC uV */ 86*4882a593Smuzhiyun 996000 1250000 87*4882a593Smuzhiyun 792000 1175000 88*4882a593Smuzhiyun 396000 1175000 89*4882a593Smuzhiyun 198000 1175000 90*4882a593Smuzhiyun >; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&ecspi4 { 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi4>; 96*4882a593Smuzhiyun cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&fec1 { 101*4882a593Smuzhiyun pinctrl-names = "default"; 102*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet1>; 103*4882a593Smuzhiyun phy-supply = <®_peri_3v3>; 104*4882a593Smuzhiyun phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 105*4882a593Smuzhiyun phy-reset-duration = <5>; 106*4882a593Smuzhiyun phy-mode = "rmii"; 107*4882a593Smuzhiyun phy-handle = <ðphy0>; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun mdio { 111*4882a593Smuzhiyun #address-cells = <1>; 112*4882a593Smuzhiyun #size-cells = <0>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun ethphy0: ethernet0-phy@0 { 115*4882a593Smuzhiyun reg = <0>; 116*4882a593Smuzhiyun max-speed = <100>; 117*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 118*4882a593Smuzhiyun interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&fec2 { 124*4882a593Smuzhiyun pinctrl-names = "default"; 125*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet2>; 126*4882a593Smuzhiyun phy-supply = <®_peri_3v3>; 127*4882a593Smuzhiyun phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 128*4882a593Smuzhiyun phy-reset-duration = <5>; 129*4882a593Smuzhiyun phy-mode = "rmii"; 130*4882a593Smuzhiyun phy-handle = <ðphy1>; 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun mdio { 134*4882a593Smuzhiyun #address-cells = <1>; 135*4882a593Smuzhiyun #size-cells = <0>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun ethphy1: ethernet1-phy@0 { 138*4882a593Smuzhiyun reg = <0>; 139*4882a593Smuzhiyun max-speed = <100>; 140*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 141*4882a593Smuzhiyun interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&flexcan1 { 147*4882a593Smuzhiyun pinctrl-names = "default"; 148*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan1>; 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&flexcan2 { 153*4882a593Smuzhiyun pinctrl-names = "default"; 154*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan2>; 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&i2c1 { 159*4882a593Smuzhiyun clock-frequency = <100000>; 160*4882a593Smuzhiyun pinctrl-names = "default"; 161*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun proximity: sx9500@28 { 165*4882a593Smuzhiyun compatible = "semtech,sx9500"; 166*4882a593Smuzhiyun reg = <0x28>; 167*4882a593Smuzhiyun pinctrl-names = "default"; 168*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sx9500>; 169*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 170*4882a593Smuzhiyun interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 171*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun pmic: pfuze100@8 { 175*4882a593Smuzhiyun compatible = "fsl,pfuze200"; 176*4882a593Smuzhiyun reg = <0x08>; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun regulators { 179*4882a593Smuzhiyun sw1a_reg: sw1ab { 180*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 181*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 182*4882a593Smuzhiyun regulator-boot-on; 183*4882a593Smuzhiyun regulator-always-on; 184*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun sw2_reg: sw2 { 188*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 189*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 190*4882a593Smuzhiyun regulator-boot-on; 191*4882a593Smuzhiyun regulator-always-on; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun sw3a_reg: sw3a { 195*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 196*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 197*4882a593Smuzhiyun regulator-boot-on; 198*4882a593Smuzhiyun regulator-always-on; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun sw3b_reg: sw3b { 202*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 203*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 204*4882a593Smuzhiyun regulator-boot-on; 205*4882a593Smuzhiyun regulator-always-on; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun snvs_reg: vsnvs { 209*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 210*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 211*4882a593Smuzhiyun regulator-boot-on; 212*4882a593Smuzhiyun regulator-always-on; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun vref_reg: vrefddr { 216*4882a593Smuzhiyun regulator-boot-on; 217*4882a593Smuzhiyun regulator-always-on; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun vgen1_reg: vgen1 { 221*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 222*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 223*4882a593Smuzhiyun regulator-always-on; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun vgen2_reg: vgen2 { 227*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 228*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun vgen3_reg: vgen3 { 232*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 233*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 234*4882a593Smuzhiyun regulator-always-on; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun vgen4_reg: vgen4 { 238*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 239*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 240*4882a593Smuzhiyun regulator-always-on; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun vgen5_reg: vgen5 { 244*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 245*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 246*4882a593Smuzhiyun regulator-always-on; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun vgen6_reg: vgen6 { 250*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 251*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 252*4882a593Smuzhiyun regulator-always-on; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&i2c3 { 259*4882a593Smuzhiyun clock-frequency = <100000>; 260*4882a593Smuzhiyun pinctrl-names = "default"; 261*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 262*4882a593Smuzhiyun status = "okay"; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&iomuxc { 266*4882a593Smuzhiyun pinctrl-names = "default"; 267*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpios>; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun pinctrl_ecspi4: ecspi4grp { 270*4882a593Smuzhiyun fsl,pins = < 271*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1 272*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1 273*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1 274*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0 275*4882a593Smuzhiyun >; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun pinctrl_enet1: enet1grp { 279*4882a593Smuzhiyun fsl,pins = < 280*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1 281*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1 282*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9 283*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9 284*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1 285*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9 286*4882a593Smuzhiyun MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038 287*4882a593Smuzhiyun /* LAN8720 PHY Reset */ 288*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0 289*4882a593Smuzhiyun /* MDIO */ 290*4882a593Smuzhiyun MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9 291*4882a593Smuzhiyun MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9 292*4882a593Smuzhiyun /* IRQ from PHY */ 293*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0 294*4882a593Smuzhiyun >; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun pinctrl_enet2: enet2grp { 298*4882a593Smuzhiyun fsl,pins = < 299*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0 300*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0 301*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0 302*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0 303*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0 304*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0 305*4882a593Smuzhiyun MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038 306*4882a593Smuzhiyun /* LAN8720 PHY Reset */ 307*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0 308*4882a593Smuzhiyun /* MDIO */ 309*4882a593Smuzhiyun MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9 310*4882a593Smuzhiyun MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9 311*4882a593Smuzhiyun /* IRQ from PHY */ 312*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0 313*4882a593Smuzhiyun >; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun pinctrl_flexcan1: flexcan1grp { 317*4882a593Smuzhiyun fsl,pins = < 318*4882a593Smuzhiyun MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 319*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 320*4882a593Smuzhiyun >; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun pinctrl_flexcan2: flexcan2grp { 324*4882a593Smuzhiyun fsl,pins = < 325*4882a593Smuzhiyun MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 326*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 327*4882a593Smuzhiyun >; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun pinctrl_gpios: gpiosgrp { 331*4882a593Smuzhiyun fsl,pins = < 332*4882a593Smuzhiyun /* reset external uC */ 333*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0 334*4882a593Smuzhiyun /* IRQ from external uC */ 335*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0 336*4882a593Smuzhiyun /* overcurrent detection */ 337*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0 338*4882a593Smuzhiyun >; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 342*4882a593Smuzhiyun fsl,pins = < 343*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 344*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 345*4882a593Smuzhiyun >; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 349*4882a593Smuzhiyun fsl,pins = < 350*4882a593Smuzhiyun MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1 351*4882a593Smuzhiyun MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1 352*4882a593Smuzhiyun >; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 356*4882a593Smuzhiyun fsl,pins = < 357*4882a593Smuzhiyun MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 358*4882a593Smuzhiyun >; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp-1 { 362*4882a593Smuzhiyun fsl,pins = < 363*4882a593Smuzhiyun /* blue LED */ 364*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1 365*4882a593Smuzhiyun >; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp-1 { 369*4882a593Smuzhiyun fsl,pins = < 370*4882a593Smuzhiyun /* green LED */ 371*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1 372*4882a593Smuzhiyun >; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun pinctrl_pwm6: pwm6grp-1 { 376*4882a593Smuzhiyun fsl,pins = < 377*4882a593Smuzhiyun /* red LED */ 378*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1 379*4882a593Smuzhiyun >; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun pinctrl_sx9500: sx9500grp { 383*4882a593Smuzhiyun fsl,pins = < 384*4882a593Smuzhiyun /* Reset */ 385*4882a593Smuzhiyun MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838 386*4882a593Smuzhiyun /* IRQ */ 387*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0 388*4882a593Smuzhiyun >; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 392*4882a593Smuzhiyun fsl,pins = < 393*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 394*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 395*4882a593Smuzhiyun >; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 399*4882a593Smuzhiyun fsl,pins = < 400*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 401*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 402*4882a593Smuzhiyun >; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun pinctrl_usb_otg1: usbotg1grp { 406*4882a593Smuzhiyun fsl,pins = < 407*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 408*4882a593Smuzhiyun >; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun pinctrl_usb_otg1_id: usbotg1idgrp { 412*4882a593Smuzhiyun fsl,pins = < 413*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 414*4882a593Smuzhiyun >; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { 418*4882a593Smuzhiyun fsl,pins = < 419*4882a593Smuzhiyun MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 420*4882a593Smuzhiyun MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 421*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 422*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 423*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 424*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 425*4882a593Smuzhiyun MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000 426*4882a593Smuzhiyun MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0 427*4882a593Smuzhiyun >; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 431*4882a593Smuzhiyun fsl,pins = < 432*4882a593Smuzhiyun MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9 433*4882a593Smuzhiyun MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9 434*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9 435*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9 436*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9 437*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9 438*4882a593Smuzhiyun >; 439*4882a593Smuzhiyun }; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 442*4882a593Smuzhiyun fsl,pins = < 443*4882a593Smuzhiyun MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9 444*4882a593Smuzhiyun MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9 445*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9 446*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9 447*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9 448*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9 449*4882a593Smuzhiyun >; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { 453*4882a593Smuzhiyun fsl,pins = < 454*4882a593Smuzhiyun MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 455*4882a593Smuzhiyun MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 456*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 457*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 458*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 459*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 460*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 461*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 462*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 463*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 464*4882a593Smuzhiyun MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 465*4882a593Smuzhiyun >; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun pinctrl_usdhc4_100mhz: usdhc4-100mhz { 469*4882a593Smuzhiyun fsl,pins = < 470*4882a593Smuzhiyun MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 471*4882a593Smuzhiyun MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 472*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 473*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 474*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 475*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 476*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 477*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 478*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 479*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 480*4882a593Smuzhiyun >; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun pinctrl_usdhc4_200mhz: usdhc4-200mhz { 484*4882a593Smuzhiyun fsl,pins = < 485*4882a593Smuzhiyun MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 486*4882a593Smuzhiyun MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 487*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 488*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 489*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 490*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 491*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 492*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 493*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 494*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 495*4882a593Smuzhiyun >; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun}; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun&pcie { 500*4882a593Smuzhiyun pinctrl-names = "default"; 501*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 502*4882a593Smuzhiyun reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; 503*4882a593Smuzhiyun reset-gpio-active-high; 504*4882a593Smuzhiyun status = "okay"; 505*4882a593Smuzhiyun}; 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun&pwm1 { 508*4882a593Smuzhiyun #pwm-cells = <2>; 509*4882a593Smuzhiyun pinctrl-names = "default"; 510*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 511*4882a593Smuzhiyun status = "okay"; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&pwm2 { 515*4882a593Smuzhiyun #pwm-cells = <2>; 516*4882a593Smuzhiyun pinctrl-names = "default"; 517*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; 518*4882a593Smuzhiyun status = "okay"; 519*4882a593Smuzhiyun}; 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun&pwm6 { 522*4882a593Smuzhiyun #pwm-cells = <2>; 523*4882a593Smuzhiyun pinctrl-names = "default"; 524*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm6>; 525*4882a593Smuzhiyun status = "okay"; 526*4882a593Smuzhiyun}; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun®_arm { 529*4882a593Smuzhiyun vin-supply = <&sw1a_reg>; 530*4882a593Smuzhiyun}; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun®_soc { 533*4882a593Smuzhiyun vin-supply = <&sw1a_reg>; 534*4882a593Smuzhiyun}; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun&snvs_poweroff { 537*4882a593Smuzhiyun status = "okay"; 538*4882a593Smuzhiyun}; 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun&uart1 { 541*4882a593Smuzhiyun pinctrl-names = "default"; 542*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&uart2 { 547*4882a593Smuzhiyun pinctrl-names = "default"; 548*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 549*4882a593Smuzhiyun status = "okay"; 550*4882a593Smuzhiyun}; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun&usbotg1 { 553*4882a593Smuzhiyun vbus-supply = <®_usb_otg1_vbus>; 554*4882a593Smuzhiyun pinctrl-names = "default"; 555*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_otg1_id>; 556*4882a593Smuzhiyun status = "okay"; 557*4882a593Smuzhiyun}; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun&usbotg2 { 560*4882a593Smuzhiyun dr_mode = "host"; 561*4882a593Smuzhiyun status = "okay"; 562*4882a593Smuzhiyun}; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun&usdhc2 { 565*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 566*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2_50mhz>; 567*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 568*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 569*4882a593Smuzhiyun cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; 570*4882a593Smuzhiyun keep-power-in-suspend; 571*4882a593Smuzhiyun status = "okay"; 572*4882a593Smuzhiyun}; 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun&usdhc4 { 575*4882a593Smuzhiyun /* hs200-mode is currently unsupported because Vccq is on 3.1V, but 576*4882a593Smuzhiyun * not on necessary 1.8V. 577*4882a593Smuzhiyun */ 578*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 579*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4_50mhz>; 580*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc4_100mhz>; 581*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc4_200mhz>; 582*4882a593Smuzhiyun bus-width = <8>; 583*4882a593Smuzhiyun keep-power-in-suspend; 584*4882a593Smuzhiyun non-removable; 585*4882a593Smuzhiyun cap-mmc-hw-reset; 586*4882a593Smuzhiyun status = "okay"; 587*4882a593Smuzhiyun}; 588