1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright (C) 2014 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 9*4882a593Smuzhiyun#include "imx6sx.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Freescale i.MX6 SoloX SDB Board"; 13*4882a593Smuzhiyun compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun stdout-path = &uart1; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@80000000 { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <0x80000000 0x40000000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun backlight_display: backlight-display { 25*4882a593Smuzhiyun compatible = "pwm-backlight"; 26*4882a593Smuzhiyun pwms = <&pwm3 0 5000000>; 27*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 28*4882a593Smuzhiyun default-brightness-level = <6>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gpio-keys { 32*4882a593Smuzhiyun compatible = "gpio-keys"; 33*4882a593Smuzhiyun pinctrl-names = "default"; 34*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun volume-up { 37*4882a593Smuzhiyun label = "Volume Up"; 38*4882a593Smuzhiyun gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; 39*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 40*4882a593Smuzhiyun wakeup-source; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun volume-down { 44*4882a593Smuzhiyun label = "Volume Down"; 45*4882a593Smuzhiyun gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 46*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 47*4882a593Smuzhiyun wakeup-source; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun vcc_sd3: regulator-vcc-sd3 { 52*4882a593Smuzhiyun compatible = "regulator-fixed"; 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_vcc_sd3>; 55*4882a593Smuzhiyun regulator-name = "VCC_SD3"; 56*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 57*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 58*4882a593Smuzhiyun gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 59*4882a593Smuzhiyun enable-active-high; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 63*4882a593Smuzhiyun compatible = "regulator-fixed"; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_otg1>; 66*4882a593Smuzhiyun regulator-name = "usb_otg1_vbus"; 67*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 68*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 69*4882a593Smuzhiyun gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 70*4882a593Smuzhiyun enable-active-high; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 74*4882a593Smuzhiyun compatible = "regulator-fixed"; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_otg2>; 77*4882a593Smuzhiyun regulator-name = "usb_otg2_vbus"; 78*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 79*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 80*4882a593Smuzhiyun gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 81*4882a593Smuzhiyun enable-active-high; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun reg_psu_5v: regulator-psu-5v { 85*4882a593Smuzhiyun compatible = "regulator-fixed"; 86*4882a593Smuzhiyun regulator-name = "PSU-5V0"; 87*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 88*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun reg_lcd_3v3: regulator-lcd-3v3 { 92*4882a593Smuzhiyun compatible = "regulator-fixed"; 93*4882a593Smuzhiyun regulator-name = "lcd-3v3"; 94*4882a593Smuzhiyun gpio = <&gpio3 27 0>; 95*4882a593Smuzhiyun enable-active-high; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun reg_peri_3v3: regulator-peri-3v3 { 99*4882a593Smuzhiyun compatible = "regulator-fixed"; 100*4882a593Smuzhiyun pinctrl-names = "default"; 101*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_peri_3v3>; 102*4882a593Smuzhiyun regulator-name = "peri_3v3"; 103*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 104*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 105*4882a593Smuzhiyun gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; 106*4882a593Smuzhiyun enable-active-high; 107*4882a593Smuzhiyun regulator-always-on; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun reg_enet_3v3: regulator-enet-3v3 { 111*4882a593Smuzhiyun compatible = "regulator-fixed"; 112*4882a593Smuzhiyun pinctrl-names = "default"; 113*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet_3v3>; 114*4882a593Smuzhiyun regulator-name = "enet_3v3"; 115*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 116*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 117*4882a593Smuzhiyun gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; 118*4882a593Smuzhiyun regulator-boot-on; 119*4882a593Smuzhiyun regulator-always-on; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun reg_pcie_gpio: regulator-pcie-gpio { 123*4882a593Smuzhiyun compatible = "regulator-fixed"; 124*4882a593Smuzhiyun pinctrl-names = "default"; 125*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie_reg>; 126*4882a593Smuzhiyun regulator-name = "MPCIE_3V3"; 127*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 128*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 129*4882a593Smuzhiyun gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; 130*4882a593Smuzhiyun enable-active-high; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun reg_lcd_5v: regulator-lcd-5v { 134*4882a593Smuzhiyun compatible = "regulator-fixed"; 135*4882a593Smuzhiyun regulator-name = "lcd-5v0"; 136*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 137*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun reg_can_en: regulator-can-en { 141*4882a593Smuzhiyun compatible = "regulator-fixed"; 142*4882a593Smuzhiyun regulator-name = "can-en"; 143*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 144*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun reg_can_stby: regulator-can-stby { 148*4882a593Smuzhiyun compatible = "regulator-fixed"; 149*4882a593Smuzhiyun regulator-name = "can-stby"; 150*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 151*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun sound { 155*4882a593Smuzhiyun compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; 156*4882a593Smuzhiyun pinctrl-names = "default"; 157*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hp>; 158*4882a593Smuzhiyun model = "wm8962-audio"; 159*4882a593Smuzhiyun ssi-controller = <&ssi2>; 160*4882a593Smuzhiyun audio-codec = <&codec>; 161*4882a593Smuzhiyun audio-routing = 162*4882a593Smuzhiyun "Headphone Jack", "HPOUTL", 163*4882a593Smuzhiyun "Headphone Jack", "HPOUTR", 164*4882a593Smuzhiyun "Ext Spk", "SPKOUTL", 165*4882a593Smuzhiyun "Ext Spk", "SPKOUTR", 166*4882a593Smuzhiyun "AMIC", "MICBIAS", 167*4882a593Smuzhiyun "IN3R", "AMIC"; 168*4882a593Smuzhiyun mux-int-port = <2>; 169*4882a593Smuzhiyun mux-ext-port = <6>; 170*4882a593Smuzhiyun hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun panel { 174*4882a593Smuzhiyun compatible = "sii,43wvf1g"; 175*4882a593Smuzhiyun backlight = <&backlight_display>; 176*4882a593Smuzhiyun dvdd-supply = <®_lcd_3v3>; 177*4882a593Smuzhiyun avdd-supply = <®_lcd_5v>; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun port { 180*4882a593Smuzhiyun panel_in: endpoint { 181*4882a593Smuzhiyun remote-endpoint = <&display_out>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun sound-spdif { 187*4882a593Smuzhiyun compatible = "fsl,imx-audio-spdif", 188*4882a593Smuzhiyun "fsl,imx6sx-sdb-spdif"; 189*4882a593Smuzhiyun model = "imx-spdif"; 190*4882a593Smuzhiyun spdif-controller = <&spdif>; 191*4882a593Smuzhiyun spdif-out; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&audmux { 197*4882a593Smuzhiyun pinctrl-names = "default"; 198*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 199*4882a593Smuzhiyun status = "okay"; 200*4882a593Smuzhiyun}; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun&fec1 { 203*4882a593Smuzhiyun pinctrl-names = "default"; 204*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet1>; 205*4882a593Smuzhiyun phy-supply = <®_enet_3v3>; 206*4882a593Smuzhiyun phy-mode = "rgmii-id"; 207*4882a593Smuzhiyun phy-handle = <ðphy1>; 208*4882a593Smuzhiyun phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 209*4882a593Smuzhiyun status = "okay"; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun mdio { 212*4882a593Smuzhiyun #address-cells = <1>; 213*4882a593Smuzhiyun #size-cells = <0>; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 216*4882a593Smuzhiyun reg = <1>; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun ethphy2: ethernet-phy@2 { 220*4882a593Smuzhiyun reg = <2>; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun}; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun&fec2 { 226*4882a593Smuzhiyun pinctrl-names = "default"; 227*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet2>; 228*4882a593Smuzhiyun phy-mode = "rgmii-id"; 229*4882a593Smuzhiyun phy-handle = <ðphy2>; 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&flexcan1 { 234*4882a593Smuzhiyun pinctrl-names = "default"; 235*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan1>; 236*4882a593Smuzhiyun xceiver-supply = <®_can_stby>; 237*4882a593Smuzhiyun status = "okay"; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun&flexcan2 { 241*4882a593Smuzhiyun pinctrl-names = "default"; 242*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan2>; 243*4882a593Smuzhiyun xceiver-supply = <®_can_stby>; 244*4882a593Smuzhiyun status = "okay"; 245*4882a593Smuzhiyun}; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun&i2c3 { 248*4882a593Smuzhiyun clock-frequency = <100000>; 249*4882a593Smuzhiyun pinctrl-names = "default"; 250*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 251*4882a593Smuzhiyun status = "okay"; 252*4882a593Smuzhiyun}; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun&i2c4 { 255*4882a593Smuzhiyun clock-frequency = <100000>; 256*4882a593Smuzhiyun pinctrl-names = "default"; 257*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c4>; 258*4882a593Smuzhiyun status = "okay"; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun codec: wm8962@1a { 261*4882a593Smuzhiyun compatible = "wlf,wm8962"; 262*4882a593Smuzhiyun reg = <0x1a>; 263*4882a593Smuzhiyun clocks = <&clks IMX6SX_CLK_AUDIO>; 264*4882a593Smuzhiyun DCVDD-supply = <&vgen4_reg>; 265*4882a593Smuzhiyun DBVDD-supply = <&vgen4_reg>; 266*4882a593Smuzhiyun AVDD-supply = <&vgen4_reg>; 267*4882a593Smuzhiyun CPVDD-supply = <&vgen4_reg>; 268*4882a593Smuzhiyun MICVDD-supply = <&vgen3_reg>; 269*4882a593Smuzhiyun PLLVDD-supply = <&vgen4_reg>; 270*4882a593Smuzhiyun SPKVDD1-supply = <®_psu_5v>; 271*4882a593Smuzhiyun SPKVDD2-supply = <®_psu_5v>; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun}; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun&pcie { 276*4882a593Smuzhiyun pinctrl-names = "default"; 277*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 278*4882a593Smuzhiyun reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; 279*4882a593Smuzhiyun vpcie-supply = <®_pcie_gpio>; 280*4882a593Smuzhiyun status = "okay"; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&lcdif1 { 284*4882a593Smuzhiyun pinctrl-names = "default"; 285*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lcd>; 286*4882a593Smuzhiyun status = "okay"; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun port { 289*4882a593Smuzhiyun display_out: endpoint { 290*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun&pwm3 { 296*4882a593Smuzhiyun #pwm-cells = <2>; 297*4882a593Smuzhiyun pinctrl-names = "default"; 298*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; 299*4882a593Smuzhiyun status = "okay"; 300*4882a593Smuzhiyun}; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun&snvs_poweroff { 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&sai1 { 307*4882a593Smuzhiyun pinctrl-names = "default"; 308*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sai1>; 309*4882a593Smuzhiyun status = "disabled"; 310*4882a593Smuzhiyun}; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun&spdif { 313*4882a593Smuzhiyun pinctrl-names = "default"; 314*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spdif>; 315*4882a593Smuzhiyun assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; 316*4882a593Smuzhiyun assigned-clock-rates = <24576000>; 317*4882a593Smuzhiyun status = "okay"; 318*4882a593Smuzhiyun}; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun&ssi2 { 321*4882a593Smuzhiyun status = "okay"; 322*4882a593Smuzhiyun}; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun&uart1 { 325*4882a593Smuzhiyun pinctrl-names = "default"; 326*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 327*4882a593Smuzhiyun status = "okay"; 328*4882a593Smuzhiyun}; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun&uart5 { /* for bluetooth */ 331*4882a593Smuzhiyun pinctrl-names = "default"; 332*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 333*4882a593Smuzhiyun uart-has-rtscts; 334*4882a593Smuzhiyun status = "okay"; 335*4882a593Smuzhiyun}; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun&usbotg1 { 338*4882a593Smuzhiyun vbus-supply = <®_usb_otg1_vbus>; 339*4882a593Smuzhiyun pinctrl-names = "default"; 340*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_otg1_id>; 341*4882a593Smuzhiyun status = "okay"; 342*4882a593Smuzhiyun}; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun&usbotg2 { 345*4882a593Smuzhiyun vbus-supply = <®_usb_otg2_vbus>; 346*4882a593Smuzhiyun dr_mode = "host"; 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&usbphy1 { 351*4882a593Smuzhiyun fsl,tx-d-cal = <106>; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&usbphy2 { 355*4882a593Smuzhiyun fsl,tx-d-cal = <106>; 356*4882a593Smuzhiyun}; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun&usdhc2 { 359*4882a593Smuzhiyun pinctrl-names = "default"; 360*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 361*4882a593Smuzhiyun non-removable; 362*4882a593Smuzhiyun no-1-8-v; 363*4882a593Smuzhiyun keep-power-in-suspend; 364*4882a593Smuzhiyun wakeup-source; 365*4882a593Smuzhiyun status = "okay"; 366*4882a593Smuzhiyun}; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun&usdhc3 { 369*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 370*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 371*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 372*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 373*4882a593Smuzhiyun bus-width = <8>; 374*4882a593Smuzhiyun cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 375*4882a593Smuzhiyun wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 376*4882a593Smuzhiyun keep-power-in-suspend; 377*4882a593Smuzhiyun wakeup-source; 378*4882a593Smuzhiyun vmmc-supply = <&vcc_sd3>; 379*4882a593Smuzhiyun status = "okay"; 380*4882a593Smuzhiyun}; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun&usdhc4 { 383*4882a593Smuzhiyun pinctrl-names = "default"; 384*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 385*4882a593Smuzhiyun cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; 386*4882a593Smuzhiyun wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; 387*4882a593Smuzhiyun status = "okay"; 388*4882a593Smuzhiyun}; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun&wdog1 { 391*4882a593Smuzhiyun pinctrl-names = "default"; 392*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 393*4882a593Smuzhiyun fsl,ext-reset-output; 394*4882a593Smuzhiyun}; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&iomuxc { 397*4882a593Smuzhiyun imx6x-sdb { 398*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 399*4882a593Smuzhiyun fsl,pins = < 400*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 401*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 402*4882a593Smuzhiyun MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 403*4882a593Smuzhiyun MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 404*4882a593Smuzhiyun MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 405*4882a593Smuzhiyun >; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun pinctrl_enet1: enet1grp { 409*4882a593Smuzhiyun fsl,pins = < 410*4882a593Smuzhiyun MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 411*4882a593Smuzhiyun MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 412*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 413*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 414*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 415*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 416*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 417*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 418*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 419*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 420*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 421*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 422*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 423*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 424*4882a593Smuzhiyun MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 425*4882a593Smuzhiyun /* phy reset */ 426*4882a593Smuzhiyun MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 427*4882a593Smuzhiyun >; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun pinctrl_enet_3v3: enet3v3grp { 431*4882a593Smuzhiyun fsl,pins = < 432*4882a593Smuzhiyun MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 433*4882a593Smuzhiyun >; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun pinctrl_enet2: enet2grp { 437*4882a593Smuzhiyun fsl,pins = < 438*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 439*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 440*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 441*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 442*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 443*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 444*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 445*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 446*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 447*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 448*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 449*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 450*4882a593Smuzhiyun >; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun pinctrl_flexcan1: flexcan1grp { 454*4882a593Smuzhiyun fsl,pins = < 455*4882a593Smuzhiyun MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 456*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 457*4882a593Smuzhiyun >; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun pinctrl_flexcan2: flexcan2grp { 461*4882a593Smuzhiyun fsl,pins = < 462*4882a593Smuzhiyun MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 463*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 464*4882a593Smuzhiyun >; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun pinctrl_gpio_keys: gpio_keysgrp { 468*4882a593Smuzhiyun fsl,pins = < 469*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 470*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 471*4882a593Smuzhiyun >; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun pinctrl_hp: hpgrp { 475*4882a593Smuzhiyun fsl,pins = < 476*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 477*4882a593Smuzhiyun >; 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 481*4882a593Smuzhiyun fsl,pins = < 482*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 483*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 484*4882a593Smuzhiyun >; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 488*4882a593Smuzhiyun fsl,pins = < 489*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 490*4882a593Smuzhiyun MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 491*4882a593Smuzhiyun >; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun pinctrl_i2c4: i2c4grp { 495*4882a593Smuzhiyun fsl,pins = < 496*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 497*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 498*4882a593Smuzhiyun >; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun pinctrl_lcd: lcdgrp { 502*4882a593Smuzhiyun fsl,pins = < 503*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 504*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 505*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 506*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 507*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 508*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 509*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 510*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 511*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 512*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 513*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 514*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 515*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 516*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 517*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 518*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 519*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 520*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 521*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 522*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 523*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 524*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 525*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 526*4882a593Smuzhiyun MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 527*4882a593Smuzhiyun MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 528*4882a593Smuzhiyun MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 529*4882a593Smuzhiyun MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 530*4882a593Smuzhiyun MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 531*4882a593Smuzhiyun MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 532*4882a593Smuzhiyun >; 533*4882a593Smuzhiyun }; 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun pinctrl_mqs: mqsgrp { 536*4882a593Smuzhiyun fsl,pins = < 537*4882a593Smuzhiyun MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 538*4882a593Smuzhiyun MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 539*4882a593Smuzhiyun >; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 543*4882a593Smuzhiyun fsl,pins = < 544*4882a593Smuzhiyun MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 545*4882a593Smuzhiyun >; 546*4882a593Smuzhiyun }; 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun pinctrl_pcie_reg: pciereggrp { 549*4882a593Smuzhiyun fsl,pins = < 550*4882a593Smuzhiyun MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 551*4882a593Smuzhiyun >; 552*4882a593Smuzhiyun }; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun pinctrl_peri_3v3: peri3v3grp { 555*4882a593Smuzhiyun fsl,pins = < 556*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 557*4882a593Smuzhiyun >; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp-1 { 561*4882a593Smuzhiyun fsl,pins = < 562*4882a593Smuzhiyun MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 563*4882a593Smuzhiyun >; 564*4882a593Smuzhiyun }; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun pinctrl_qspi2: qspi2grp { 567*4882a593Smuzhiyun fsl,pins = < 568*4882a593Smuzhiyun MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 569*4882a593Smuzhiyun MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 570*4882a593Smuzhiyun MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 571*4882a593Smuzhiyun MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 572*4882a593Smuzhiyun MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 573*4882a593Smuzhiyun MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 574*4882a593Smuzhiyun MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 575*4882a593Smuzhiyun MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 576*4882a593Smuzhiyun MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 577*4882a593Smuzhiyun MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 578*4882a593Smuzhiyun MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 579*4882a593Smuzhiyun MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 580*4882a593Smuzhiyun >; 581*4882a593Smuzhiyun }; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun pinctrl_vcc_sd3: vccsd3grp { 584*4882a593Smuzhiyun fsl,pins = < 585*4882a593Smuzhiyun MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 586*4882a593Smuzhiyun >; 587*4882a593Smuzhiyun }; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun pinctrl_sai1: sai1grp { 590*4882a593Smuzhiyun fsl,pins = < 591*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 592*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 593*4882a593Smuzhiyun MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 594*4882a593Smuzhiyun MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 595*4882a593Smuzhiyun MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 596*4882a593Smuzhiyun >; 597*4882a593Smuzhiyun }; 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun pinctrl_spdif: spdifgrp { 600*4882a593Smuzhiyun fsl,pins = < 601*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 602*4882a593Smuzhiyun >; 603*4882a593Smuzhiyun }; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 606*4882a593Smuzhiyun fsl,pins = < 607*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 608*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 609*4882a593Smuzhiyun >; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 613*4882a593Smuzhiyun fsl,pins = < 614*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 615*4882a593Smuzhiyun MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 616*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 617*4882a593Smuzhiyun MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 618*4882a593Smuzhiyun >; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun pinctrl_usb_otg1: usbotg1grp { 622*4882a593Smuzhiyun fsl,pins = < 623*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 624*4882a593Smuzhiyun >; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun pinctrl_usb_otg1_id: usbotg1idgrp { 628*4882a593Smuzhiyun fsl,pins = < 629*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 630*4882a593Smuzhiyun >; 631*4882a593Smuzhiyun }; 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun pinctrl_usb_otg2: usbot2ggrp { 634*4882a593Smuzhiyun fsl,pins = < 635*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 636*4882a593Smuzhiyun >; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 640*4882a593Smuzhiyun fsl,pins = < 641*4882a593Smuzhiyun MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 642*4882a593Smuzhiyun MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 643*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 644*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 645*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 646*4882a593Smuzhiyun MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 647*4882a593Smuzhiyun >; 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 651*4882a593Smuzhiyun fsl,pins = < 652*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 653*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 654*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 655*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 656*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 657*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 658*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 659*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 660*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 661*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 662*4882a593Smuzhiyun MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 663*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 664*4882a593Smuzhiyun >; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 668*4882a593Smuzhiyun fsl,pins = < 669*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 670*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 671*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 672*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 673*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 674*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 675*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 676*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 677*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 678*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 679*4882a593Smuzhiyun >; 680*4882a593Smuzhiyun }; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 683*4882a593Smuzhiyun fsl,pins = < 684*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 685*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 686*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 687*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 688*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 689*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 690*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 691*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 692*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 693*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 694*4882a593Smuzhiyun >; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 698*4882a593Smuzhiyun fsl,pins = < 699*4882a593Smuzhiyun MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 700*4882a593Smuzhiyun MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 701*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 702*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 703*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 704*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 705*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 706*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 707*4882a593Smuzhiyun >; 708*4882a593Smuzhiyun }; 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 711*4882a593Smuzhiyun fsl,pins = < 712*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 713*4882a593Smuzhiyun >; 714*4882a593Smuzhiyun }; 715*4882a593Smuzhiyun }; 716*4882a593Smuzhiyun}; 717